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[미국특허] Semiconductor device with an airtight space formed internally within a hollow package 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/02
  • H01L-023/12
  • H01L-029/40
출원번호 US-0155539 (1993-11-22)
우선권정보 JP-0193617 (1990-07-21); JP-0193465 (1990-07-21)
발명자 / 주소
  • Katayama Shigeru (Sodegaura JPX) Tominaga Kaoru (Sodegaura JPX) Yoshitake Junichi (Sodegaura JPX)
출원인 / 주소
  • Mitsui Petrochemical Industries, Ltd. (Tokyo JPX 03)
인용정보 피인용 횟수 : 240  인용 특허 : 0

초록 ▼

This invention relates to a package construction of a semiconductor device, and provides a semiconductor device in which a vapor-impermeable moistureproof plate is embedded in a bottom surface of a hollow package or an inner surface wallthicknesswise therefrom to provide an excellent moisture-proofn

대표청구항 ▼

A semiconductor device comprising: a hollow package including an airtight space formed in a central portion of said hollow package; a semiconductor chip; and a vapor-impermeable moistureproof plate including an island portion connected to a lead frame by a support lead, said island portion provided

이 특허를 인용한 특허 (240) 인용/피인용 타임라인 분석

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  153. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
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  154. Kim, Gi Jeong; Kim, Jae Yoon; Lee, Kyu Won, Semiconductor device including leadframe with downsets.
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  155. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
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  156. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
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  157. Yukinobu Wataya JP; Hideto Isono JP, Semiconductor device including solid state imaging device.
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  158. Moriga Namiki,JPX, Semiconductor device mounted in resin sealed container.
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  159. Ohmori Jun,JPX ; Iwasaki Hiroshi,JPX ; Takahashi Takuya,JPX ; Jin Takanori,JPX ; Fukuda Masatoshi,JPX, Semiconductor device with a thickness of 1 MM or less.
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  160. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
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  161. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
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  162. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
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  163. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
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  164. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
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  165. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
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  166. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
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  167. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
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  168. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
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  169. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
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  170. Jae Hak Yee KR; Young Suk Chung KR; Jae Jin Lee KR; Terry Davis ; Chung Suk Han KR; Jae Hun Ku KR; Jae Sung Kwak KR; Sang Hyun Ryu KR, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  171. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  172. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  173. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  174. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  175. Jung,Dae Hoon; Lee,Seok Won; Park,Sang Bae, Semiconductor package and process for making the same.
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  176. Lee, Sun Goo; Jang, Sang Jae; Lee, Choon Heung; Yoshida, Akito, Semiconductor package capable of die stacking.
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  177. Lee, Sun Goo; Lee, Choon Heung; Lee, Sang Ho, Semiconductor package exhibiting efficient lead placement.
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  178. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
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  179. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
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  180. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
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  181. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
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  182. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
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  183. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
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  184. Paek, Jong Sik, Semiconductor package including flip chip.
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  185. Paek,Jong Sik, Semiconductor package including flip chip.
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  186. Foster, Donald Craig, Semiconductor package including isolated ring structure.
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  187. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
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  188. Yang, Jun Young; Lee, Sun Goo; Lee, Choon Heung, Semiconductor package including low temperature co-fired ceramic substrate.
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  189. Miks, Jeffrey Alan, Semiconductor package including ring structure connected to leads with vertically downset inner ends.
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  190. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.
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  191. Yang,Sung Jin; Ha,Sun Ho; Kim,Ki Ho; Son,Sun Jin, Semiconductor package with chamfered corners and method of manufacturing the same.
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  192. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
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  193. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
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  194. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
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  195. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
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  196. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
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  197. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
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  198. Lee, Choon Heung; Foster, Donald C.; Choi, Jeoung Kyu; Kim, Wan Jong; Youn, Kyong Hoon; Lee, Sang Ho; Lee, Sun Goo, Semiconductor package with increased number of input and output pins.
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  199. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
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  200. Jeong, Jung Ho; Hong, Jong Chul; Kim, Eun Deok, Semiconductor package with optimized leadframe bonding strength.
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  201. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
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  202. Hu, Tom; Davis, Terry W.; Bancod, Ludovico, Semiconductor package with singulation crease.
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  203. Hsu, Cheng-Ho; Chang, Yi-Hua; Liou, Jen-Cheng, Semiconductor packaging structure.
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  204. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  205. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  206. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
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  207. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
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  208. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
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  209. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
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  210. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
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  211. Tsuda,Tadaaki; Yamamoto,Yasushi; Kawahara,Hiroshi; Takahashi,Yoshihiro; Sakai,Minoru, Surface acoustic wave device.
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  212. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  213. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
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  214. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
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  215. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
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  216. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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  217. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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  218. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
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  219. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
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  220. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  221. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  222. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
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  223. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
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  224. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
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  225. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
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  226. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
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  227. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  228. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  229. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  230. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  231. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  232. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  233. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  234. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
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  235. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
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  236. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
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  237. Li Zong-Fu ; Sengupta Kabul ; Thompson Deborah L., Windowed non-ceramic package having embedded frame.
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  238. Li, Zong-Fu; Sengupta, Kabul; Thompson, Deborah L., Windowed non-ceramic package having embedded frame.
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  239. Li,Zong Fu; Sengupta,Kabul; Thompson,Deborah L., Windowed package having embedded frame.
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  240. Li,Zong Fu; Sengupta,Kabul; Thompson,Deborah L., Windowed package having embedded frame.
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