[특허]Sidewall doping technique for SOI transistors

Sidewall doping technique for SOI transistors 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/265 H01L-021/302 H01L-021/76
출원번호	US-0001875 (1993-01-08)
발명자 / 주소	Sundaresan Ravishankar (Garland TX)
출원인 / 주소	Texas Instruments Incorporated (Dallas TX 02)
인용정보	피인용 횟수 : 89 인용 특허 : 0

초록

A method of sidewall doping is described wherein the implantation of the dopant is done after the high temperature sidewall oxidation formation. Therefore, this method allows high concentrations of the dopant to be retained along the sidewall thus decreasing the corner coupling.

대표청구항 ▼

A process for fabricating a semiconductor-on-insulator integrated circuit structure, comprising the steps of: providing a substrate having at a surface thereof a monocrystalline semiconductor material layer overlying an insulator layer; depositing an oxide layer, covering said monocrystalline semiconductor layer; providing a pattered masking layer over said oxide layer, comprising a first and a second masking material layer, said masking layer being patterned to cover predetermined portions of said monocrystalline semiconductor layer where active devices are to be formed; depositing additional said second masking material, which forms sidewall spacers on said patterned masking layer, so that said patterned masking layer with said spacers covers a larger fraction of said semiconductor layer than was covered by said masking layer alone; etching away at least some portions of said monocrystalline semiconductor material layer, using said patterned masking layer and said spacers as a mask, forming a mesa; forming sidewall insulation filaments on said monocrystalline semiconductor material mesa, subsequent to said etching away at least some portions of said monocrystalline semiconductor material, so that said monocrystalline semiconductor layer mesa with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone; removing all but said first masking material layer of the patterned masking layers,; implanting a dopant into at least some of the portions of said semiconductor material which are not covered by said first masking material layer to form doped mesa edges, subsequent to said forming of the sidewall insulation filaments and subsequent to said removing all but aid first masking layer step; removing said first masking material layer, and; fabricating active devices in said mesas.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Sidewall doping technique for SOI transistors 원문보기

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Sidewall doping technique for SOI transistors 원문보기

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