[특허]Intelligent cache memory and prefetch method based on CPU data fetching characteristics

Intelligent cache memory and prefetch method based on CPU data fetching characteristics 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-012/08
출원번호	US-0901803 (1992-06-22)
발명자 / 주소	Westberg Thomas E. (Sudbury MA)
출원인 / 주소	Sun Microsystems, Inc. (Mountain View CA 02)
인용정보	피인용 횟수 : 66 인용 특허 : 0

초록 ▼

An intelligent cache memory system and associated method for reducing a central processing unit (CPU) idle time. The system performs prefetches based on data fetching characteristics of the CPU. The system includes cache control logic, a first and a second cache memory, each having a number of cache lines, and a first and a second cache tag array, each having cache tag entries corresponding to the cache lines. The cache tag entries comprise cache tags and valid bits. The cache tag entries of the second cache tag array further comprise interest bits. In addition to their traditional functions, the cache tags and the valid bits, in conjunction with the interest bits, are used to track the data fetching history of the CPU. For each read cycle, the cache control logic returns the data being fetched by the CPU from either the first or the second cache memory or the main memory. Additionally, the cache control logic initiates prefetch and updates the data fetching history conditionally. The data fetched from either the second cache memory or the main memory are also stored in the first cache memory, whereas the data prefetched are stored in the second cache memory. Prefetch is conditioned on the data fetching history, while data fetching history update is conditioned on where the data requested by the CPU are fetched. As a result, CPU idle time is further reduced and system performance is further improved.

대표청구항 ▼

In a computer system comprising a central processing unit (CPU) coupled to a main memory, a method for reducing CPU idle time and improving system performance based on data fetching characteristics of said CPU, said method comprising the steps of: a) detecting read cycles provided by said CPU to access data stored in said main memory, said read cycles include source addresses indicating memory locations of data to be fetched for said read cycles; b) fetching data for each of the detected read cycles from a selected one of a first level cache memory, a second level cache memory and said main memory, as each of the read cycles is detected: wherein said first level cache memory comprises a plurality of cache lines having corresponding cache tags and valid bits, said second level cache memory comprises a plurality of cache lines having corresponding cache tags, valid bits and interest bits; said source addresses are cached in said first level cache memory if said source addresses match said cache tags of said cache lines of said first level cache memory and said valid bits of said cache lines of said first level cache memory are set to valid, said source addresses are cached in said second level cache memory if said source addresses match said cache tags of said cache lines of said second level cache memory and said valid bits of said matching cache lines of said second level cache memory are set to valid; said data to be fetched for said detected read cycles are fetched from said first level cache memory if said source addresses are cached in said first level cache memory at the time said read are detected said data to be fetched for said detected read cycles are fetched from said second level cache memory if said source addresses of said detected read cycles are not cached in said first level cache memory but are cached in said second level cache memory at the time said read cycles are detected, said data to be fetched for said detected read cycles are fetched from said main memory if said source addresses of said detected read cycles are not cached in said first level cache memory or said second level cache memory at the time said read cycles are detected; the fetched data for said detected read cycles being stored into said first level cache memory if said fetched data for said detected read cycles are fetched from either said second level cache memory or said main memory: c) prefetching data anticipated to be fetched by said CPU subsequent to each of said detected read cycles from said main memory if said data to be fetched for said detected read cycles are fetched from either said second level cache memory or said main memory, and a predetermined prefetch threshold is met at the time; said predetermined threshold being met if said source addresses match said cache tags of said cache lines of said second level cache memory and said interest bits of said matching cache lines of said second level cache memory are set to interested; the prefetched data for said detected read cycles being stored in said second level cache memory as the data is prefetched; d) updating said cache tags, valid bits and interest bits of said matching cache lines of said second level cache memory as the data to be fetched for each of said detected read cycles is fetched if said data to be fetched for said detected read cycles are fetched from either said second level cache memory or said main memory; e) returning the fetched data for each of said detected read cycles to said CPU as the data is fetched: f) detecting write cycles provided by said CPU to store data in said main memory; g) performing standard write operations for data to be written for each of said detected write cycles as said write cycles are detected; and h) resetting said cache tags valid bits. and interest bits of said matching cache lines of said second level cache memory conditionally as said standard write operations are performed for each of said detected write cycles the resettings being conditioned on whether the data is to be written in said first level cache memory, said second level cache memory or said main memory.

이 특허를 인용한 특허 (66)

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Intelligent cache memory and prefetch method based on CPU data fetching characteristics 원문보기

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Intelligent cache memory and prefetch method based on CPU data fetching characteristics 원문보기

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