[특허]Integrated register allocation, instruction scheduling, instruction reduction and loop unrolling

Integrated register allocation, instruction scheduling, instruction reduction and loop unrolling 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-012/00
출원번호	US-0982962 (1992-11-30)
발명자 / 주소	Smith Kevin J. (Boulder Creek CA) Kenner Hugh R. (Cupertino CA) Savage William A. (Milpitas CA) Kwong Alice (Los Altos CA)
출원인 / 주소	Intel Corporation (Santa Clara CA 02)
인용정보	피인용 횟수 : 56 인용 특허 : 0

초록 ▼

An improved register allocator, an improved instruction scheduler, an instruction combiner, and an improved loop unroller is provided to the code generator of a compiler of a computer system. Both the improved instruction scheduler and the improved loop unroller support a “preliminary”and a “final”mode of operation. Upon invocation, the improved register allocator determines and prioritizes regions of the program being compiled. Next, the improved register allocator, in cooperation with the improved instruction scheduler, the instruction combiner, and the improved loop unroller, determines the optimal partitioning for global and local registers for each region. Then, the improved register allocator allocates registers to each region based on the determined number of global registers for the region. After allocating registers for each region, the improved register allocator merges the regions together. The improved loop unroller and the improved instruction scheduler are then invoked successively in “final”mode to unroll the various loops and schedule the instructions being generated.

대표청구항 ▼

In a computer system comprising a plurality of registers and a plurality of pipelines for parallel and overlapping execution of instructions, a method for allocating said registers to instructions being generated for a program being compiled, unrolling loops of said program, and scheduling said instructions being generated for execution, said method comprising the steps of: a) allocating global registers to said instructions being generated for a first time using all registers of said computer system; b) scheduling said instructions being generated for a first time, allocating local registers using a copy of all registers of said computer system; c) determining optimal number of times to unroll loops of said program; d) determining optimal partitioning of said registers of said computer system into global and local registers, said partitioning determination being made based on the relative utilities of each of said registers to global register allocation and instruction scheduling; e) allocating global registers to said instructions being generated for a second time using said registers of said computer system partitioned to be global registers; f) unrolling said loops; and g) scheduling said instructions being generated for a second time, allocating local registers using said registers of said computer system partitioned to be local registers.

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Integrated register allocation, instruction scheduling, instruction reduction and loop unrolling 원문보기

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Integrated register allocation, instruction scheduling, instruction reduction and loop unrolling 원문보기

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