이 특허를 인용한 특허 (239)

1. Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Adder-rounder circuitry for specialized processing block in programmable logic device.

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2. Langhammer, Martin, Angular range reduction in an integrated circuit device.

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3. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.

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4. Ting, Benjamin S., Architecture and interconnect scheme for programmable logic circuits.

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5. Ting,Benjamin S., Architecture and interconnect scheme for programmable logic circuits.

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6. McClintock Cameron ; Ngo Ninh ; Altaf Risa ; Cliff Richard G., Architectures for programmable logic devices.

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7. Kaptanoglu, Sinan, Block connector splitting in logic block of a field programmable gate array.

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8. Kaptanoglu, Sinan, Block level routing architecture in a field programmable gate array.

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9. Kaptanoglu,Sinan, Block level routing architecture in a field programmable gate array.

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10. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

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11. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

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12. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

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13. Langhammer, Martin, Calculation of trigonometric functions in an integrated circuit device.

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14. Reddy Srinivas T. ; Zaveri Ketan ; Lane Christopher F. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B. ; Mejia Manuel ; Cliff Richard G., Circuitry and methods for internal interconnection of programmable logic devices.

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15. Srinivas T. Reddy ; Ketan Zaveri ; Christopher F. Lane ; Andy L. Lee ; Cameron R. McClintock ; Bruce B. Pedersen ; Manuel Mejia ; Richard G. Cliff, Circuitry and methods for internal interconnection of programmable logic devices.

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16. Langhammer,Martin; Prasad,Nitin, Circuitry for arithmetically accumulating a succession of arithmetic values.

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17. Cliff Richard G., Coarse-grained look-up table architecture.

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18. Langhammer, Martin, Combined adder and pre-adder for high-radix multiplier circuit.

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19. Langhammer, Martin, Combined floating point adder and subtractor.

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20. Mauer, Volker, Combined interpolation and decimation filter for programmable logic device.

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21. Langhammer, Martin, Computing floating-point polynomials in an integrated circuit device.

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22. Langhammer, Martin; Pasca, Bogdan, Computing floating-point polynomials in an integrated circuit device.

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23. Jennings ; III Earle W. (Richardson TX) Landers George H. (Mountain View CA), Configurable logic networks.

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24. Evans,Brian P.; Hunt,Jeffery Scott, Configurable matrix architecture.

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25. Langhammer, Martin, Configuring a programmable integrated circuit device to perform matrix multiplication.

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26. Langhammer, Martin, Configuring floating point operations in a programmable device.

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27. Langhammer, Martin, Configuring floating point operations in a programmable logic device.

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28. Manohararajah, Valavan; Lewis, David, Configuring programmable integrated circuit device resources as processing elements.

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29. Leung, Wai-Bor; Lui, Henry Y., DSP block for implementing large multiplier on a programmable integrated circuit device.

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30. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.

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31. Langhammer, Martin, DSP processor architecture with write datapath word conditioning and analysis.

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32. Pistorius, Erhard Joachim; Hutton, Michael D., Dedicated function block interfacing with general purpose function blocks on integrated circuits.

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33. Plants, William C., Deglitching circuits for a radiation-hardened static random access memory based programmable architecture.

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34. Plants,William C., Deglitching circuits for a radiation-hardened static random access memory based programmable architecture.

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35. Plants,William C., Deglitching circuits for a radiation-hardened static random access memory based programmable architecture.

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36. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

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37. Langhammer, Martin; Starr, Gregory; Hwang, Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

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38. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

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39. Langhammer,Martin; Starr,Gregory; Hwang,Chiao Kai, Devices and methods with programmable logic and digital signal processing regions.

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40. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.

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41. Demirsoy, Suleyman Sirri; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.

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42. Demirsoy, Suleyman; Yi, Hyun, Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering.

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43. Langhammer, Martin, Digital signal processing circuitry with redundancy and ability to support larger multipliers.

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44. Langhammer, Martin; Lin, Yi-Wen; Streicher, Keone, Digital signal processing circuitry with redundancy and bidirectional data paths.

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45. Langhammer, Martin, Discrete Fourier Transform in an integrated circuit device.

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46. Langhammer, Martin, Double-clocked specialized processing block in an integrated circuit device.

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47. Pedersen Bruce B., Driver circuitry for programmable logic devices.

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48. Srinivas T. Reddy ; Christopher F. Lane ; Manuel Mejia ; Richard G. Cliff ; Kerry Veenstra, Dual port programmable logic device variable depth and width memory array.

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49. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel ; Cliff Richard G. ; Veenstra Kerry, Dual-port programmable logic device variable depth and width memory array.

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50. Lane, Christopher F.; Powell, Giles V.; Yeung, Wayne; Sung, Chiakang; Pedersen, Bruce B., Efficient arrangement of interconnection resources on programmable logic devices.

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51. Lane, Christopher F.; Powell, Giles V.; Yeung, Wayne; Sung, Chiakang; Pedersen, Bruce B., Efficient arrangement of interconnection resources on programmable logic devices.

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52. Pellizzer,Fabio; De Sandre,Guido; Bez,Roberto, Field programmable gate array device.

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53. New Bernard J., Field programmable gate array having a dedicated internal bus system.

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54. Xiao Ping ; Yin YiYian P., High density PLD structure with flexible logic built-in blocks.

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55. Xiao Ping ; Yin Yiyian P., High-density programmable logic device with flexible local connections and multiplexer based global interconnections.

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56. Chou, Shin-I, High-rate interpolation or decimation filter in integrated circuit device.

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57. Langhammer, Martin, Implementing division in a programmable integrated circuit device.

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58. Langhammer, Martin, Implementing large multipliers in a programmable integrated circuit device.

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59. Langhammer, Martin, Implementing mixed-precision floating-point operations in a programmable integrated circuit device.

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60. Langhammer, Martin, Implementing multipliers in a programmable integrated circuit device.

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61. Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; Jefferson David Edward, Input/output circuitry for programmable logic devices.

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62. Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; Jefferson David Edward, Input/output circuitry for programmable logic devices.

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63. Huang Joseph ; Cliff Richard G. ; Reddy Srinivas T., Input/output interface circuitry for programmable logic array integrated circuit devices.

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64. Huang Joseph ; Cliff Richard G. ; Reddy Srinivas T., Input/output interface circuitry for programmable logic array integrated circuit devices.

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65. Gregoire Francois ; Madurawe Raminda ; Thalapaneni Guru, Integrated circuit pad structures.

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66. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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67. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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68. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection and input/output resources for programable logic integrated circuit devices.

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69. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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70. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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71. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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72. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Hutton,Michael; Maruri,Victor; Patel,Rakesh; Kazarian,Peter J.; Leaver,Andrew; Mendel,David W.; Park,Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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73. Ngai,Tony; Pedersen,Bruce; Shumarayev,Sergey; Schleicher,James; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection and input/output resources for programmable logic integrated circuit devices.

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74. Tony Ngai ; Bruce Pedersen ; Sergey Shumarayev ; James Schleicher ; Wei-Jen Huang ; Michael Hutton ; Victor Maruri ; Rakesh Patel ; Peter J. Kazarian ; Andrew Leaver ; David W. Mendel ; Ji, Interconnection and input/output resources for programmable logic integrated circuit devices.

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75. James Schleicher ; James Park ; Sergey Shumarayev ; Bruce Pedersen ; Tony Ngai ; Wei-Jen Huang ; Victor Maruri ; Rakesh Patel, Interconnection resources for programmable logic integrated circuit devices.

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76. Schleicher, James; Park, James; Shumarayev, Sergey; Pedersen, Bruce; Ngai, Tony; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection resources for programmable logic integrated circuit devices.

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77. Schleicher, James; Park, James; Shumarayev, Sergey; Pedersen, Bruce; Ngai, Tony; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection resources for programmable logic integrated circuit devices.

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78. Schleicher, James; Park, James; Shumarayev, Sergey; Pedersen, Bruce; Ngai, Tony; Huang, Wei-Jen; Maruri, Victor; Patel, Rakesh, Interconnection resources for programmable logic integrated circuit devices.

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79. Schleicher,James; Park,Jim; Shumarayev,Sergey; Pederson,Bruce; Ngai,Tony; Huang,Wei Jen; Maruri,Victor; Patel,Rakesh, Interconnection resources for programmable logic integrated circuit devices.

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80. Lee Fung Fung, Interleaved interconnect for programmable logic array devices.

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81. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

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82. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

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83. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

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84. Langhammer, Martin; Tharmalingam, Kumara, Large multiplier for programmable logic device.

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85. Pedersen Bruce B., Logic cell for programmable logic devices.

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86. David W. Mendel ; Richard G. Cliff, Logic element for a programmable logic integrated circuit.

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87. Mendel David W. ; Cliff Richard G., Logic element for a programmable logic integrated circuit.

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88. Wilson Stanley ; Chan King W. ; Frappier Mark, Logic function module for field programmable array.

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89. Wei-Jen Huang ; Sergey Shumarayev ; Tony Ngai ; Bruce Pedersen, Logic module circuitry for programmable logic devices.

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90. Galbraith Douglas C. ; El Gamal Abbas ; Greene Jonathan W., Logic module with configurable combinational and sequential blocks.

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91. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Wang Bonnie I., Logic region resources for programmable logic devices.

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92. Langhammer, Martin, Matrix decomposition in an integrated circuit device.

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93. Kurtz, Brian L., Matrix operations in an integrated circuit device.

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94. Langhammer, Martin, Matrix operations in an integrated circuit device.

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95. Langhammer,Martin; Steinke,Gregory R.; Schlacter,Guy R.; Neidermeier,Bernd, Method and apparatus for protecting designs in SRAM-based programmable logic devices.

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96. Langhammer, Martin, Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like.

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97. Pedersen, Bruce B.; Reese, Dirk A.; Joyce, Juju, Method and apparatus for securing a programmable device using a kill switch.

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98. Pedersen, Bruce B.; Reese, Dirk A.; Joyce, Juju, Method and apparatus for securing a programmable device using a kill switch.

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99. Doshi, Alok Shreekant; Pedersen, Bruce B., Method and apparatus for securing configuration scan chains of a programmable device.

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100. Reese, Dirk A.; Joyce, JuJu, Method and apparatus for securing programming data of a programmable device.

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101. Reese, Dirk A.; Joyce, JuJu, Method and apparatus for securing programming data of a programmable device.

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102. Sung Chiakang ; Wang Bonnie I., Method and apparatus for securing programming data of programmable logic device.

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103. Pani, Peter M.; Ting, Benjamin S., Method and apparatus for universal program controlled bus architecture.

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104. Pani,Peter M.; Ting,Benjamin S., Method and apparatus for universal program controlled bus architecture.

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105. Mauer, Volker; Demirsoy, Suleyman Sirri, Method for configuring a finite impulse response filter in a programmable logic device.

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106. Tharmalingam,Kumara, Method for programming programmable logic device having specialized functional blocks.

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107. Agrawal Om P. ; Sharpe-Geisler Bradley A., Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device.

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108. New,Bernard J.; Carter,William S., Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames.

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109. Pedersen Bruce B., Methods for allocating circuit design portions among physical circuit portions.

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110. Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Chang Herman M. ; Tran Giap H., Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources.

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111. Nazarian Hagop A. ; Douglass Stephen M. ; Graf W. Alfred ; Raza S. Babar ; Rajan Sundar ; Borzin Shiva Sorooshian ; Neuman Darren, Methods for maximizing routability in a programmable interconnect matrix having less than full connectability.

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112. Nazarian Hagop A. ; Douglass Stephen M. ; Graf W. Alfred ; Raza S. Babar ; Rajan Sundar ; Borzin Shiva Sorooshian ; Newman Darren, Methods for maximizing routability in a programmable interconnect matrix having less than full connectability.

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113. Tse John (El Cerrito CA) Mendel David W. (Sunnyvale CA), Methods for partitioning circuits in order to allocate elements among multiple circuit groups.

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114. Langhammer, Martin, Methods for specifying processor architectures for programmable integrated circuits.

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115. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

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116. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

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117. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.

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118. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.

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119. Agrawal Om P. ; Sharpe-Geisler Bradley A., Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices.

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120. Williams, Timothy; Kutz, Harold; Snyder, Warren; Wright, David G., Multifunction input/output circuit.

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121. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.

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122. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.

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123. Nance,Scott S.; Sheppard,Douglas P.; Sawyer,Nicholas J., Multiport RAM with programmable data port configuration.

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124. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.

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125. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.

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126. Hutton,Michael D.; Pedersen,Bruce; Kaptanoglu,Sinan; Lewis,David; Vanderhoek,Tim, Organizations of logic modules in programmable logic devices.

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127. Hutton,Michael D; Pedersen,Bruce; Kaptanoglu,Sinan; Lewis,David; Vanderhoek,Tim, Organizations of logic modules in programmable logic devices.

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128. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., PCI-compatible programmable logic devices.

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129. Cliff Richard G. ; Huang Joseph ; Sung Chiakang ; Wang Bonnie I., PCI-compatible programmable logic devices.

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130. Cliff, Richard G.; Heile, Francis B.; Huang, Joseph; Mendel, David W.; Pendersen, Bruce B.; Sung, Chiakang; Veenstra, Kerry; Wang, Bonnie I., PCI-compatible programmable logic devices.

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131. Cliff,Richard G; Heile,Francis B; Huang,Joseph; Mendel,David W; Pedersen,Bruce B; Sung,Chiakang; Veenstra,Kerry; Wang,Bonnie I, PCI-compatible programmable logic devices.

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132. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.

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133. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.

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134. Mendel David Wolk (Sunnyvale CA), Product term based programmable logic array devices with reduced control memory requirements.

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135. Eric M. Shiflet, Programmable I/O cells with multiple drivers.

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136. Shiflet Eric M., Programmable I/O cells with multiple drivers.

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137. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.

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138. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.

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139. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.

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140. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.

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141. Leong William W. (San Francisco CA) Cliff Richard G. (Milpitas CA) McClintock Cameron (Mountain View CA), Programmable logic array device with grouped logic regions and three types of conductors.

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142. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.

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143. Mendel David W., Programmable logic array devices with enhanced interconnectivity between adjacent logic regions.

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144. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.

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145. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.

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146. McClintock Cameron ; Leong William ; Cliff Richard G. ; Ahanin Bahram, Programmable logic array devices with interconnect lines of various lengths.

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147. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit architectures.

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148. Cliff Richard G. ; Heile Francis B. ; Sung Chiakang ; Wang Bonnie I. ; Pedersen Bruce B., Programmable logic array integrated circuit architectures.

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149. Richard G. Cliff ; Francis B. Heile ; Joseph Huang ; Christopher F. Lane ; Fung Fung Lee ; Cameron McClintock ; David W. Mendel ; Ninh D. Ngo ; Bruce B. Pedersen ; Srinivas T. Reddy ; Chiak, Programmable logic array integrated circuit architectures.

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150. Cliff Richard G. (Milpitas CA) Reddy Srinivas T. (Santa Clara CA) Raman Rina (Fremont CA) Cope L. Todd (San Jose CA) Huang Joseph (San Jose CA) Pedersen Bruce B. (San Jose CA), Programmable logic array integrated circuit devices.

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151. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array integrated circuit devices.

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152. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.

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153. Cliff Richard G. ; Reddy Srinivas T. ; Raman Rina ; Cope L. Todd ; Huang Joseph ; Pedersen Bruce B., Programmable logic array integrated circuit devices.

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154. Cliff, Richard G.; Reddy, Srinivas T.; Jefferson, David Edward; Raman, Rina; Cope, L. Todd; Lane, Christopher F.; Huang, Joseph; Heile, Francis B.; Pedersen, Bruce B.; Mendel, David Wolk; Lytle, Crai, Programmable logic array integrated circuit devices.

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155. Richard G. Cliff ; Srinivas T. Reddy ; David Edward Jefferson ; Rina Raman ; L. Todd Cope ; Christopher F. Lane ; Joseph Huang ; Francis B. Heile ; Bruce B. Pedersen ; David Wolk Mendel ; C, Programmable logic array integrated circuit devices.

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156. Lee Fung F. (Milpitas CA) Tse John (El Cerrito CA), Programmable logic array integrated circuit devices with flexible carry chains.

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157. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lane Christopher F. ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Ngo Ninh D. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ;, Programmable logic array integrated circuit devices with interleaved logic array blocks.

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158. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic array integrated circuit devices with interleaved logic array blocks.

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159. Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig Schilling; Heile, Francis B.; Pedersen, Bruce B.; Veenstra, Kerry, Programmable logic array integrated circuits.

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160. Richard G. Cliff ; Cameron McClintock ; William Leong, Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks.

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161. Reddy Srinivas T. (Santa Clara CA) Sung Chiakang (Milpitas CA) Wang Bonnie I-Keh (Cupertino CA), Programmable logic array integrated circuits with improved interconnection conductor utilization.

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162. Leong William (San Francisco CA) McClintock Cameron (Mountain View CA) Cliff Richard G. (Milpitas CA), Programmable logic array integrated circuits with interconnection conductors of overlapping extent.

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163. Cliff Richard G. ; Reddy Srinivas T. ; Jefferson David E. ; Raman Rina ; Cope L. Todd ; Lane Christopher F. ; Huang Joseph ; Heile Francis B. ; Pedersen Bruce B. ; Mendel David W. ; Lytle Craig S. ; , Programmable logic array intergrated circuit devices.

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164. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Lee Fung Fung ; McClintock Cameron ; Mendel David W. ; Pedersen Bruce B. ; Reddy Srinivas T. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., Programmable logic device architectures.

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165. Jefferson, David E.; McClintock, Cameron; Schleicher, James; Lee, Andy L.; Mejia, Manuel; Pedersen, Bruce B.; Lane, Christopher F.; Cliff, Richard G.; Reddy, Srinivas T., Programmable logic device architectures with super-regions having logic regions and a memory region.

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166. David E. Jefferson ; Cameron McClintock ; James Schleicher ; Andy L. Lee ; Manuel Mejia ; Bruce B. Pederson ; Christopher F. Lane ; Richard G. Cliff ; Srinivas T. Reddy, Programmable logic device architectures with super-regions having logic regions and memory region.

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167. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

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168. Langhammer, Martin; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

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169. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

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170. Langhammer,Martin; Hwang,Chiao Kai; Starr,Gregory, Programmable logic device including multipliers and configurations thereof to reduce resource utilization.

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171. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel, Programmable logic device memory array circuit having combinable single-port memory arrays.

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172. Reddy Srinivas T. ; Lane Christopher F. ; Mejia Manuel, Programmable logic device memory array circuit having combinable single-port memory arrays.

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173. Shumarayev, Sergey Y.; Patel, Rakesh H., Programmable logic device multispeed I/O circuitry.

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174. Ketan Zaveri ; Christopher F. Lane ; Srinivas T. Reddy ; Andy L. Lee ; Cameron R. McClintock ; Bruce B. Pedersen, Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits.

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175. Zaveri Ketan ; Lane Christopher F. ; Reddy Srinivas T. ; Lee Andy L. ; McClintock Cameron R. ; Pedersen Bruce B., Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits.

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176. Zaveri, Ketan; Lane, Christopher F.; Reddy, Srinivas T.; Lee, Andy L.; McClintock, Cameron R.; Pedersen, Bruce B., Programmable logic device with circuitry for observing programmable logic circuit signals and for preloading programmable logic circuits.

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177. Lee Andy L. ; Cliff Richard G. ; Jefferson David ; McClintock Cameron ; Altaf Kurosu R., Programmable logic device with enhanced multiplexing capabilities in interconnect resources.

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178. Lee Andy L. ; Cliff Richard G. ; Jefferson David ; McClintock Cameron ; Altaf Kurosu R., Programmable logic device with enhanced multiplexing capabilities in interconnect resources.

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179. Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.

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180. Reddy Srinivas T. ; Cliff Richard G. ; Lane Christopher F. ; Zaveri Ketan H. ; Mejia Manuel M. ; Jefferson David ; Pedersen Bruce B. ; Lee Andy L., Programmable logic device with hierarchical interconnection resources.

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181. Reddy, Srinivas T.; Cliff, Richard G.; Lane, Christopher F.; Zaveri, Ketan H.; Mejia, Manuel M.; Jefferson, David; Pedersen, Bruce B.; Lee, Andy L., Programmable logic device with hierarchical interconnection resources.

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182. Reddy, Srinivas T.; Cliff, Richard G.; Lane, Christopher F.; Zaveri, Ketan H.; Mejia, Manuel M.; Jefferson, David; Pedersen, Bruce B.; Lee, Andy L., Programmable logic device with hierarchical interconnection resources.

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183. Srinivas T. Reddy ; Richard G. Cliff ; Christopher F. Lane ; Ketan H. Zaveri ; Manuel M. Mejia ; David Jefferson ; Bruce B. Pedersen ; Andy L. Lee, Programmable logic device with hierarchical interconnection resources.

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184. Langhammer, Martin, Programmable logic device with routing channels.

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185. Langhammer,Martin, Programmable logic device with routing channels.

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186. Langhammer,Martin, Programmable logic device with routing channels.

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187. Langhammer,Martin, Programmable logic device with routing channels.

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188. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.

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189. Langhammer, Martin; Zheng, Leon; Hwang, Chiao Kai; Starr, Gregory, Programmable logic device with specialized functional block.

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190. Langhammer, Martin, Programmable logic device with specialized multiplier blocks.

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191. Andy L. Lee ; Christopher F. Lane ; Bruce B. Pedersen, Programmable logic devices with enhanced multiplexing capabilities.

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192. Lee Andy L. ; Lane Christopher F. ; Pedersen Bruce B., Programmable logic devices with enhanced multiplexing capabilities.

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193. Lee Andy L. ; Lane Christopher F. ; Pedersen Bruce B., Programmable logic devices with enhanced multiplexing capabilities.

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194. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.

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195. Langhammer, Martin; Prasad, Nitin, Programmable logic devices with function-specific blocks.

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196. Mendel David W., Programmable logic integrated circuit architecture incorporating a global shareable expander.

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197. Mendel David W., Programmable logic integrated circuit architecture incorporating a global shareable expander.

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198. Mendel David W., Programmable logic integrated circuit architecture incorporating a lonely register.

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199. Mendel David W., Programmable logic integrated circuit architecture incorporating a lonely register.

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200. Wong Myron Wai, Programmable voltage supply circuitry.

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201. Chu Michael Hsiao-Ming (Fremont CA) Patel Rakesh H. (Cupertino CA), Programming programmable transistor devices using state machines.

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202. Chu Michael Hsiao-Ming ; Patel Rakesh H., Programming programmable transistor devices using state machines.

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203. Langhammer, Martin, QR decomposition in an integrated circuit device.

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204. Mauer, Volker, QR decomposition in an integrated circuit device.

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205. Pedersen Bruce B., Routing in programmable logic devices using shared distributed programmable logic connectors.

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206. Langhammer, Martin; Schleicher, II, James G., Security core using soft key.

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207. Reese Dirk A. ; Wong Myron W. ; Costello John C., Sense amplifier with individually optimized high and low power modes.

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208. Pedersen, Bruce B., Setting security features of programmable logic devices.

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209. Pedersen, Bruce B., Setting security features of programmable logic devices.

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210. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.

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211. Kocher, Paul C.; Jun, Benjamin C.; Jaffe, Joshua M., Specialized circuitry for cryptographic authentication and other purposes.

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212. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.

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213. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.

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214. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.

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215. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.

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216. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.

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217. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.

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218. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.

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219. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.

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220. Morse, Douglas C.; Lee, Clement, Structure and method for implementing wide multiplexers.

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221. Lewis, David M.; Betz, Vaughn; Leventis, Paul; Chan, Michael; McClintock, Cameron R.; Lee, Andy L.; Lane, Christopher F.; Reddy, Srinivas T.; Cliff, Richard, System and method for optimizing routing lines in a programmable logic device.

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222. Tran Nghia ; Li Ying Xuan ; Balicki Janusz ; Costello John, System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to m.

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223. Tran,Nghia; Li,Ying Xuan; Balicki,Janusz; Costello,John, System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly.

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224. Pedersen, Bruce B., Systems and methods for detecting and mitigating programmable logic device tampering.

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225. Pedersen, Bruce B., Systems and methods for detecting and mitigating programmable logic device tampering.

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226. Lim, Chooi Pei; Plofsky, Jordan; Tan, Yee Liang; Toong, Teik Tiong, Systems including an I/O stack and methods for fabricating such systems.

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227. MacArthur James ; Lacey Timothy M., Techniques and circuits for high yield improvements in programmable devices using redundant logic.

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228. MacArthur James ; Lacey Timothy, Techniques and circuits for high yield improvements in programmable devices using redundant routing resources.

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229. MacArthur James ; Lacey Timothy M., Techniques and circuits for high yield improvements in programmable devices using redundant routing resources.

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230. Cliff Richard G. ; Reddy Srinivas T. ; Papaliolios Andreas, Techniques for programming programmable logic array devices.

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231. Cliff Richard G. ; Reddy Srinivas T. ; Veenstra Kerry ; Papaliolios Andreas ; Sung Chiakang ; Terrill Richard Shaw ; Raman Rina ; Bielby Robert Richard Noel, Techniques for programming programmable logic array devices.

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232. Richard G. Cliff ; Srinivas T. Reddy ; Kerry Veenstra ; Andreas Papaliolios ; Chiakang Sung ; Richard Shaw Terrill ; Rina Raman ; Robert Richard Noel Bielby, Techniques for programming programmable logic array devices.

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233. Veenstra Kerry (San Jose CA) Bielby Robert Richard Noel (Pleasonton CA), Techniques for programming programmable logic array devices.

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234. Pedersen Bruce B., Tri-Statable input/output circuitry for programmable logic.

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235. Pedersen Bruce B., Tri-statable input/output circuitry for programmable logic.

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236. Sung Chiakang ; Chang Wanli ; Huang Joseph ; Cliff Richard G., Variable depth and width memory device.

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237. Sung, Chiakang; Chang, Wanli; Huang, Joseph; Cliff, Richard G.; Cope, L. Todd; McClintock, Cameron R.; Leong, William; Watson, James A.; Ahanin, Bahram, Variable depth and width memory device.

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238. Pedersen,Bruce B, Versatile RAM for a programmable logic device.

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239. Pedersen,Bruce B, Versatile RAM for programmable logic device.

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