이 특허를 인용한 특허 (22)

1. Masahiro Kamoshida JP; Haruki Toda JP; Tsuneaki Fuse JP; Yukihito Oowaki JP, Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal.

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2. Koester, Thorsten, Circuit and method for controllably delaying an input signal, and microscope, and method for controlling a microscope.

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3. Toda Haruki,JPX, Clock control circuit.

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4. Toda Haruki,JPX, Clock control circuit.

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5. Toda Haruki,JPX, Clock control circuit.

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6. Lin-Shih Liu ; Syed Babar Raza ; Hagop Nazarian ; George M. Ansel ; Stephen M. Douglass ; Jeffrey Scott Hunt, High speed configuration independent programmable macrocell.

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7. Heyne Patrick,DEX, Integrated circuit with adjustable delay unit.

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8. Bunce, Paul A.; Davis, John D.; Henderson, Diana M.; Vora, Jigar J., Internal bypassing of memory array devices.

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9. Bunce, Paul A.; Davis, John D.; Henderson, Diana M.; Vora, Jigar J., Jam latch for latching memory array output data.

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10. Dreps, Daniel Mark; Ferraiolo, Frank David; Hao, Jing Fang, Linear delay element providing linear delay steps.

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11. Dragula, Joshua M.; Montrose, Charles J., Memory tester design for soft error rate (SER) failure analysis.

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12. Bunce, Paul A.; Davis, John D.; Henderson, Diana M.; Vora, Jigar J., Port enable signal generation for gating a memory array device output.

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13. Huang Chi-Jung ; Li Ken Ming, Programmable delay timing calibrator for high speed data interface.

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14. Thomas W. Voshell ; R. Brent Lindsay, Programmable pulse generator and method for using same.

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15. Voshell Thomas W. ; Lindsay R. Brent, Programmable pulse generator and method for using same.

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16. Fagan, John L.; Bossard, Mark, Selectable delay pulse generator.

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17. Bunce, Paul A.; Davis, John D.; Henderson, Diana M.; Vora, Jigar J., Split voltage level restore and evaluate clock signals for memory address decoding.

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18. Okajima, Yoshinori, Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof.

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19. Okajima,Yoshinori, Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof.

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20. Okajima,Yoshinori, Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof.

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21. Foley, David P., Timing generator for generating high resolution pulses having arbitrary widths.

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22. Lee,Andy L.; Lai,Gary; Zhang,Changsong; Betz,Vaughn; Fung,Ryan, Variable delay circuitry.

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