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Reconfigurable computer interface and method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0017222 (1993-02-12)
발명자 / 주소
  • Reagle Dennis J. (Riverside CA) Bolstad Gregory D. (Orange CA)
출원인 / 주소
  • Hughes Aircraft Company (Los Angeles CA 02)
인용정보 피인용 횟수 : 80  인용 특허 : 0

초록 ▼

A reconfigurable computer interface for use in interfacing a first subsystem to a second subsystem including a reconfigurable state machine mechanism for generating a plurality of interface control signals in accordance with a state table in response to a plurality of mode control signals. A first m

대표청구항 ▼

A general purpose, reconfigurable parallel-to-parallel interface system for interfacing a first data bus from a first digital subsystem to a second data bus from a second digital subsystem, the interface system comprising: buffer memory storage means for providing temporary storage of a plurality of

이 특허를 인용한 특허 (80)

  1. Tasler, Michael L., Analog data generating and processing device for use with a personal computer.
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  2. Tasler, Michael, Analog data generating and processing device having a multi-use automatic processor.
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  3. Tasler, Michael, Analog data generating and processing device having a multi-use automatic processor.
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  4. Lumpkin Todd Wayne ; Williams Timothy Lee, Apparatus and method for high speed data and command transfer over an interface.
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  5. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd, Bus systems and reconfiguration methods.
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  6. Vorbach, Martin, Chip including memory element storing higher level memory data on a page by page basis.
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  7. Sachs,Howard G., Circuit group design methodologies.
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  8. Vorbach, Martin; Münch, Robert, Circuit having a multidimensional structure of configurable cells that include multi-bit-wide inputs and outputs.
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  9. Vorbach, Martin; Nuckel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  10. Vorbach, Martin; Nückel, Armin, Configurable logic integrated circuit having a multidimensional structure of configurable elements.
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  11. Shaila Hanrahan ; Christopher E. Phillips, Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit.
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  12. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  13. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  14. Vorbach, Martin; Thomas, Alexander, Data processing device and method.
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  15. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
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  16. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing method and device.
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  17. Vorbach, Martin; Becker, Jürgen; Weinhardt, Markus; Baumgarte, Volker; May, Frank, Data processing system having integrated pipelined array data processor.
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  18. Vorbach, Martin; Münch, Robert, Data processor having disabled cores.
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  19. Harris Kenneth M., Data storage subsystem having apparatus for enabling concurrent housekeeping processing while an input/output data transfer occurs.
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  20. Fletcher, Mitch; Kreider, Thom; Dawson, John; Clelland, Julee, Deterministic remote interface unit emulator.
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  21. Vorbach, Martin, Device including a field having function cells and information providing cells controlled by the function cells.
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  22. Authement, Shawn P.; Bosien, Kevin A.; Drinnan, David S.; Excoffier, Franck; Vo, Nhan Q.; Walls, Andrew D., Dynamically modifiable component model.
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  23. Martel Sylvain ; Lafontaine Serge R. ; Hunter Ian W., Dynamically reconfigurable hardware system for real-time control of processes.
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  24. Asprey Robert R. ; Kirshtein Philip M. ; Lusk Thomas V., Extended length differentially driven analog video link.
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  25. Surico,Stefano, Finite state machine interface has arbitration structure to store command generated by internal circuits during evaluation phase of state machine for FLASH EEPROM device.
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  26. Holst John Christian ; Wendell Dennis Lee, Handshake circuit and operating method for self-resetting circuits.
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  27. Vorbach, Martin; May, Frank, Hardware definition method including determining whether to implement a function as hardware or software.
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  28. Wilt, Nicholas; Gray, Scott; Fletcher, Mitch, High integrity data bus fault detection using multiple signal components.
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  29. Vorbach, Martin; Münch, Robert, I/O and memory bus system for DFPS and units with two- or multi-dimensional programmable cell architectures.
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  30. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  31. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  32. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
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  33. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  34. Harrison David Michael ; Ii Alison ; McCutcheon Dadario, Method and processing interface for transferring data between host systems and a packetized processing system.
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  35. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  36. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  37. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
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  38. Lin Zhongru Julia ; Malik Nadeem ; Narayanaswami Chandrasekhar ; Saha Avijit ; St. Onge Brett Adam, Method for implementing state machine using link lists by dividing each one of the combinations into an initial section,.
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  39. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  40. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  41. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  42. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.
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  43. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  44. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  45. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  46. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  47. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  48. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  50. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
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  51. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
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  52. Vorbach, Martin, Multiprocessor having associated RAM units.
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  53. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
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  54. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  56. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
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  57. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
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  58. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
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  59. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
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  60. Chalopin, Herve; Tabaries, Laurent, Programmable control interface device.
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  62. Leddy, Thomas, Re-configurable electrical connectors.
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  65. Fletcher, Mitch; Sloat, Jef; Gregg, Michael R., Re-configurable multi-purpose digital interface.
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  71. Vorbach, Martin, Reconfigurable sequencer structure.
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  72. Vorbach, Martin, Reconfigurable sequencer structure.
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  73. Vorbach, Martin, Reconfigurable sequencer structure.
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  74. Trimberger Stephen M., Reprogrammable instruction set accelerator.
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  75. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.
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  76. Vorbach, Martin; Bretz, Daniel, Router.
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  77. Bell David B. ; Dwelley David M.,SGX, Self-configuring interface circuitry, including circuitry for identifying a protocol used to send signals to the interface circuitry, and circuitry for receiving the signals using the identified prot.
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  78. Goodnow Kenneth Joseph ; Thygesen Dana John, System and method for asynchronous dual bus conversion using double state machines.
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