이 특허를 인용한 특허 (42)

1. Agarwal, Vishnu K.; Sandhu, Gurtej S., Boron incorporated diffusion barrier material.

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2. Agarwal, Vishnu K.; Sandhu, Gurtej S., Boron incorporated diffusion barrier material.

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3. Agarwal, Vishnu K.; Sandhu, Gurtej S., Boron incorporated diffusion barrier material.

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4. Agarwal, Vishnu K.; Sandhu, Gurtej S., Boron incorporated diffusion barrier material.

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5. Agarwal,Vishnu K.; Sandhu,Gurtej S., Boron incorporated diffusion barrier material.

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6. Agarwal,Vishnu K.; Sandhu,Gurtej S., Boron incorporated diffusion barrier material.

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7. Hu Yungjun Jeff, Conductive material for integrated circuit fabrication.

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8. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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9. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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10. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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11. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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12. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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13. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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14. Hu, Yungjun Jeff, Conductive material for integrated circuit fabrication.

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15. Hu,Yungjun Jeff, Conductive material for integrated circuit fabrication.

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16. Hanson David A., Electrical means for extracting layer to layer registration.

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17. Fischer Paul J. ; Korleski Joseph, Electronic chip package.

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18. Fischer, Paul J.; Korleski, Joseph E., Electronic chip package.

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19. Noddin David B., Laser apparatus having improved via processing rate.

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20. Swenson Edward J. ; Sun Yunlong ; Harris Richard S., Laser based method and system for integrated circuit repair or reconfiguration.

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21. Cooney, III,Edward C.; Motsiff,William T., Method and apparatus for selectively altering dielectric properties of localized semiconductor device regions.

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22. Coomer, Boyd L., Method and system to manufacture stacked chip devices.

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23. Koblinger Otto,DEX ; Stoffler Werner,DEX, Method for providing a metallization layer on an insulating layer and for opening through holes in the said insulating.

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24. Hanson David A., Method for reducing via inductance in an electronic assembly and article.

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25. Noddin David B. ; Hutchins Donald G., Method for using fiducial schemes to increase nominal registration during manufacture of laminated circuit.

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26. Noddin David B., Method for using photoabsorptive coatings and consumable copper to control exit via redeposit as well as diameter variance.

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27. Noddin David B. ; Gorrell Robin E. ; Leaf Michael R., Method for using ultrasonic treatment in combination with UV-lasers to enable plating of high aspect ratio micro-vias.

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28. Pagani, Alberto, Method of filling probe indentations in contact pads.

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29. Noddin David B., Method of sequential laser processing to efficiently manufacture modules requiring large volumetric density material rem.

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30. Noddin David B., Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques.

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31. Ghandi, Jaspreet S.; Yates, Don L.; Sun, Yangyang, Methods for forming a semiconductor structure.

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32. Coster, Michael T.; DiRocco, Mark A.; Gambino, Jeffrey P.; Peterson, Kirk D., Methods for testing integrated circuits of wafer and testing structures for integrated circuits.

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33. Noddin David B., Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias.

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34. Noddin David B., Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias.

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35. Noddin David B., Multiple frequency processing to minimize manufacturing variability of high aspect ratio micro through-vias.

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36. Pagani, Alberto, Probe pad with indentation.

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37. Burrell, Lloyd G.; Wong, Kwong H.; Kelly, Adreanne A.; McKnight, Samuel R., Semiconductor device having a composite layer in addition to a barrier layer between copper wiring and aluminum bond pad.

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38. Noddin David B., Semiconductor flip chip package.

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39. Pagani, Alberto; Ziglioli, Federico Giovanni, Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure.

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40. Gandhi, Jaspreet S.; Yates, Don L.; Sun, Yangyang, Semiconductor structures comprising a dielectric material having a curvilinear profile.

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41. Saran Mukul ; Martin Charles A., System and method for reinforcing a bond pad.

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42. Dunaway Thomas J. ; Spielberger Richard K., Test and tear-away bond pad design.

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