IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0289671
(1994-08-12)
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발명자
/ 주소 |
- Chien Sun-Chieh (Hsin-Chu TWX) Wu Tzong-Shien (Hsin-Chu TWX)
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| 출원인 / 주소 |
- United Micro Electronics Corporation (Hsinchu TWX 03)
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| 인용정보 |
피인용 횟수 :
91 인용 특허 :
0 |
초록
▼
A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over t
A method for making sub-micron MOS (Metal Oxide Semiconductor) devices, which do not suffer from hot carrier effect, and having improved short-channel effect and improved performance, is described. A silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over the P-well and N-well regions is provided. The P-well region is implanted, in a substantially vertical direction, with a first conductivity-imparting dopant. Gate structures are formed over the P-well and N-well regions. A second conductivity-imparting dopant is implanted, at a large angle to the plane of the silicon substrate, that is of opposite conductivity to the first conductivity-imparting dopant, into the P-well and N-well regions, masked by the gate structures. The N-well region is implanted, in a substantially vertical direction, with a third conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. Sidewall spacers are formed on the gate structures. The P-well region is implanted, in a substantially vertical direction, with a fourth conductivity-imparting dopant, of the same conductivity as the second conductivity-imparting dopant. The N-well region is implanted, in a substantially vertical direction, with a fifth conductivity-imparting dopant, of the same conductivity as the first conductivity-imparting dopant. The silicon substrate is heated to drive in the dopants.
대표청구항
▼
A method of forming metal oxide semiconductor (MOS) devices, comprising the steps of: providing a silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over said P-well and N-well regions; implanting, in a substantially vertical direction, said P-well region w
A method of forming metal oxide semiconductor (MOS) devices, comprising the steps of: providing a silicon substrate with field isolation regions, P-well and N-well regions, and an oxide layer over said P-well and N-well regions; implanting, in a substantially vertical direction, said P-well region with a first conductivity-imparting dopant; forming gate structures over said P-well and N-well regions; implanting, at a large angle to the plane of said silicon substrate, a second conductivity-imparting dopant that is of opposite conductivity to said first conductivity-imparting dopant, into said P-well and N-well regions, masked by said gate structures; implanting, in a substantially vertical direction, said N-well region with a third conductivity-imparting dopant, of same conductivity as said first conductivity-imparting dopant; forming sidewall spacers on said gate structures; implanting, in a substantially vertical direction, said P-well region with a fourth conductivity-imparting dopant, of same conductivity as said second conductivity-imparting dopant; implanting, in a substantially vertical direction, said N-well region with a fifth conductivity-imparting dopant, of same conductivity as said first conductivity-imparting dopant; and heating said silicon substrate to drive in said dopants.
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