[특허]Packaging and interconnect system for integrated circuits

[미국특허] Packaging and interconnect system for integrated circuits 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H05K-003/34
출원번호	US-0060406 (1993-05-11)
발명자 / 주소	Griswold Bradley L. (San Jose CA) Ho Chung W. (Monte Sereno CA) Robinette Jr. William C. (Los Altos CA)
출원인 / 주소	Micromodule Systems, Inc. (Cupertino CA 02)
인용정보	피인용 횟수 : 53 인용 특허 : 0

초록 ▼

A thin MCM packaging structure and technique is provided in which a thin film decal interconnect circuit is fabricated on a thin aluminum wafer. The thin-film decal interconnect employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die. A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities to hold one or more die to be mounted on the MCM structure. The die are oriented with their pads in contact with contact pads on the thin-film decal interconnect to which they are bonded and the cavities are filled with a liquid encapsulant and cured. The composite structure may be lapped down to minimize overall package thickness and to expose the backsides of the integrated circuit die for thermal management.

대표청구항 ▼

A multichip module packaging structure comprising: a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors; at least one integrated circuit die disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die having a first surface bonded to said first surface of said thin film multilayer interconnect circuit in a position such that said plurality of first bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one integrated circuit die, said at least one integrated circuit die including a plurality of I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of I/O connection pads wire bonded to corresponding ones of said plurality of first bonding pads of said thin film multilayer interconnect circuit.

이 특허를 인용한 특허 (53) 인용/피인용 타임라인 분석

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Crane ; Jr. Stanford W. ; Portuondo Maria M., Method of manufacturing a semiconductor chip carrier.
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Kenji Ohsawa JP; Hidetoshi Kusano JP, Method of producing a semiconductor chip having an underplate metal layer.
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A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
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[미국특허] Packaging and interconnect system for integrated circuits 원문보기

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[미국특허] Packaging and interconnect system for integrated circuits 원문보기

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