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Programmable logic device which stores more than one configuration and means for switching configurations 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0231009 (1994-04-20)
발명자 / 주소
  • Ong Randy T. (Cupertino CA)
출원인 / 주소
  • Xilinx, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 444  인용 특허 : 0

초록 ▼

A programmable logic device includes a configuration memory expanded to store two or more complete sets of configuration data. A switch on the output of the configuration memory controls the selection of the configuration data applied to the configurable logic block. Each configurable logic block ha

대표청구항 ▼

A programable array comprising: a configuration memory having a first storage means for storing a first set of configuration data, a second storage means for storing a second set of configuration data and a switching means coupled for outputting one of the first set and second set of configuration d

이 특허를 인용한 특허 (444)

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  162. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  163. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with configuration contexts.
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  164. Mirsky, Ethan; French, Robert; Eslick, Ian, Local control of multiple context processing elements with major contexts and minor contexts.
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  165. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  166. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  167. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  168. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logical cell array and bus system.
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  169. Gonzalez,Ricardo E.; Johnson,Scott; Taylor,Derek, Long instruction word processing with instruction extensions.
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  170. Clinton Kim P. N. ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Seidel Victor Paul ; Zittritsch Terrance John, Memory cells for field programmable memory array.
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  171. Naoya Watanabe JP; Akira Yamazaki JP, Memory system capable of supporting different memory devices and a memory device used therefor.
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  172. Redgrave, Jason; Schmit, Herman, Method and apparatus for accessing contents of memory cells.
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  173. Redgrave, Jason, Method and apparatus for accessing stored data in a reconfigurable IC.
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  174. Redgrave,Jason, Method and apparatus for accessing stored data in a reconfigurable IC.
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  175. Trimberger,Stephen M., Method and apparatus for address and data line usage in a multiple context programmable logic device.
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  176. Mirsky Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.
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  177. Mirsky, Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.
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  178. Mirsky,Ethan A., Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements.
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  179. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple cont.
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  180. Ethan Mirsky ; Robert French ; Ian Eslick, Method and apparatus for controlling contexts of multiple context processing elements in a network of multiple context processing elements.
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  181. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.
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  182. Caldwell, Andrew; Schmit, Herman; Teig, Steven, Method and apparatus for decomposing functions in a configurable IC.
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  183. Steiner,Glenn C., Method and apparatus for error mitigation of programmable logic device configuration memory.
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  184. Steiner,Glenn C., Method and apparatus for error mitigation of programmable logic device configuration memory.
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  185. Caldwell, Andrew; Teig, Steven, Method and apparatus for function decomposition.
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  186. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
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  187. Rohe, Andre; Teig, Steven, Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit.
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  188. Trimberger,Stephen M., Method and apparatus for modular redundancy with alternative mode of operation.
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  189. Trimberger,Stephen M., Method and apparatus for multiple context and high reliability operation of programmable logic devices.
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  190. Redgrave, Jason; Caldwell, Andrew; Teig, Steven, Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC.
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  191. Redgrave, Jason; Hutchings, Brad; Schmit, Herman; Teig, Steven, Method and apparatus for performing shifting in an integrated circuit.
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  192. Pugh, Daniel J., Method and apparatus for performing two's complement multiplication.
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  193. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for position independent reconfiguration in a network of multiple context processing elements.
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  194. Redgrave, Jason, Method and apparatus for reduced power cell.
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  195. Mirsky Ethan ; French Robert ; Eslick Ian, Method and apparatus for retiming in a network of multiple context processing elements.
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  196. Mirsky, Ethan; French, Robert; Eslick, Ian, Method and apparatus for retiming in a network of multiple context processing elements.
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  197. Mirsky,Ethan; French,Robert; Eslick,Ian, Method and apparatus for retiming in a network of multiple context processing elements.
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  198. John A. Harding ; David A. Schwartz ; Lap-Wai Chow, Method and apparatus for selectively performing a plurality of logic operations and memory functions.
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  199. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  200. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  201. Aldebert Jeane-Paul,FRX ; Basso Claude,FRX ; Calvignac Jean,FRX ; Chemla Paul,FRX ; Orsatti Daniel,FRX ; Verplanken Fabrice,FRX ; Zunino Jean-Claude,FRX, Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device.
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  202. Snyder, Warren; Rouse, Mark, Method and system for programming a memory device.
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  203. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
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  204. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  205. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  206. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  207. Vorbach, Martin; May, Frank; Nückel, Armin, Method for debugging reconfigurable architectures.
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  208. Vorbach,Martin, Method for debugging reconfigurable architectures.
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  209. Vorbach,Martin; May,Frank; N체ckel,Armin, Method for debugging reconfigurable architectures.
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  210. Son, Jung-Bo; Yu, Hee-Jung; Choi, Eun-Young; Yoon, Chan-Ho; Lee, Il-Gu; Lyu, Deuk-Su; Jeon, Tae-hyun; Min, Seung-Wook; Ryu, Kwhang-Hyun; Noh, Kyoung-Ju; Kim, Yun-Joo; Song, Kyoung-Hee; Lee, Sok-Kyu; Bang, Seung-Chan; Hwang, Seung-Ku, Method for digital system modeling by using higher software simulator.
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  211. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
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  212. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  213. Teig, Steven, Method for manufacturing a programmable system in package.
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  214. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.
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  215. Vorbach, Martin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  216. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  217. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
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  218. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  219. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  220. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
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  221. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  222. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Method of mapping a user design defined for a user design cycle to an IC with multiple sub-cycle reconfigurable circuits.
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  223. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Method of operating a field programmable memory array with a field programmable gate array.
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  224. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Method of processing data with an array of data processors according to application ID.
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  225. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  226. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  227. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  228. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  229. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  230. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  231. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
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  232. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  233. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  234. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
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  235. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
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  236. Trimberger Stephen M. (San Jose CA) Carberry Richard A. (Los Gatos CA) Johnson Robert A. (San Jose CA) Wong Jennifer (Fremont CA), Method of time multiplexing a programmable logic device.
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  237. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
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  238. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
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  239. Thorp, Tyler; Haukness, Brent, Methods and apparatus for employing redundant arrays to configure non-volatile memory.
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  240. Thorp, Tyler; Haukness, Brent, Methods and apparatus for employing redundant arrays to configure non-volatile memory.
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  241. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  242. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  243. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  244. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
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  245. Vorbach, Martin, Methods and devices for treating and/or processing data.
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  246. Krumel,Andrew K., Methods for packet filtering including packet invalidation if packet validity determination not timely made.
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  247. Krumel, Andrew K., Methods for updating the configuration of a programmable packet filtering device including a determination as to whether a packet is to be junked.
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  248. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  249. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  250. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  251. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.
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  252. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.
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  253. Snyder, Warren S., Microcontroller programmable system on a chip with programmable interconnect.
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  254. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
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  255. McDonald, John; Pearson, Jon; Ogami, Kenneth; Anderson, Doug, Model for a hardware device-independent method of defining embedded firmware for programmable systems.
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  256. Walstrum, Jr.,James A.; Wennekamp,Wayne E.; Edwards,Eric E., Multi-boot configuration of programmable devices.
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  257. Mirsky,Ethan; French,Robert; Eslick,Ian, Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements.
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  258. Vorbach, Martin; Baumgarte, Volker; May, Frank; Nuckel, Armin, Multi-processor bus and cache interconnection system.
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  259. Vorbach, Martin, Multi-processor with selectively interconnected memory units.
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  260. Rupp, Charle' R., Multi-scale programmable array.
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  261. Rupp,Charle' R., Multi-scale programmable array.
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  262. Reddy, Srinivas; Jefferson, David; Lane, Christopher F.; Santurkar, Vikram; Cliff, Richard, Multiple size memories in a programmable logic device.
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  263. Vorbach, Martin, Multiprocessor having associated RAM units.
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  264. Vorbach, Martin; Baumgarte, Volker, Multiprocessor having runtime adjustable clock and clock dependent power supply.
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  265. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.
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  266. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.
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  267. Schmit, Herman; Butts, Michael; Hutchings, Brad L.; Teig, Steven, Non-sequentially configurable IC.
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  268. Kutz, Harold, Numerical band gap.
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  269. Karp, James; Hart, Michael J., Operating a programmable integrated circuit with functionally equivalent configuration bitstreams.
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  270. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  271. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  272. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  273. Rohe, Andre; Teig, Steven, Operational cycle assignment in a configurable IC.
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  274. Rohe,Andre; Teig,Steven, Operational cycle assignment in a configurable IC.
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  275. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
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  276. Rohe, Andre; Teig, Steven; Schmit, Herman; Redgrave, Jason; Caldwell, Andrew, Operational time extension.
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  277. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.
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  278. Krumel,Andrew K., PLD-based packet filtering methods with PLD configuration data update of filtering rules.
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  279. Snyder, Warren S.; Mar, Monte, PSOC architecture.
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  280. Snyder, Warren; Mar, Monte, PSOC architecture.
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  281. Snyder, Warren S.; Mar, Monte, PSoC architecture.
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  282. Snyder, Warren S.; Mar, Monte, PSoC architecture.
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  283. Walstrum, Jr.,James A.; Knapp,Steven K.; Wennekamp,Wayne E., Parallel interface for configuring programmable devices.
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  284. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
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  285. Patel Rakesh H. ; Norman Kevin A., Partially reconfigurable programmable logic device.
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  286. Pugh, Daniel J.; Redgrave, Jason; Caldwell, Andrew, Performing mathematical and logical operations in multiple sub-cycles.
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  287. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  288. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  289. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
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  290. Ogami, Kenneth Y., Power management architecture, method and configuration system.
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  291. Ogami, Kenneth Y., Power management architecture, method and configuration system.
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  292. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).
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  293. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
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  294. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
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  295. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
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  296. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
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  297. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
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  298. Graf W. Alfred, Programmable I/O cell with data conversion capability.
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  299. Graf W. Alfred, Programmable I/O cell with data conversion capability.
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  300. Gould Scott Whitney ; Iadanza Joseph Andrew ; Keyser ; III Frank Ray ; Zittritsch Terrance John, Programmable address decoder for field programmable memory array.
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  301. Iadanza Joseph Andrew ; Keyser ; III Frank Ray, Programmable bit line drive modes for memory arrays.
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  302. Trimberger, Stephen M., Programmable interconnect element and method of implementing a programmable interconnect element.
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  303. Motomura Masato,JPX, Programmable logic IC having memories for previously storing a plurality of configuration data and a method of reconfigurating same.
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  304. Craig S. Lytle ; Donald F. Faria, Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory.
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  306. Cliff Richard G. ; Cope L. Todd ; Mc Clintock Cameron R. ; Leong William ; Watson James A. ; Huang Joseph ; Ahanin Bahram, Programmable logic array integrated circuits.
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  310. Cliff, Richard G.; Ahanin, Bahram; Lytle, Craig Schilling; Heile, Francis B.; Pedersen, Bruce B.; Veenstra, Kerry, Programmable logic array integrated circuits.
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  312. Kao,Oliver C.; Kunnari,Nancy D., Programmable logic auto write-back.
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  313. Arnold, Jeffrey Mark; Banta, Gareld Howard; Johnson, Scott Daniel; Wang, Albert R., Programmable logic configuration for instruction extensions.
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  316. Schultz, David P.; Hung, Lawrence C.; Goetting, F. Erich, Programmable logic device capable of preserving state data during partial or complete reconfiguration.
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  317. Schultz, David P.; Hung, Lawrence C.; Goetting, F. Erich, Programmable logic device capable of preserving user data during partial or complete reconfiguration.
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  318. Tony K. Ngai ; Rakesh H. Patel ; Srinivas T. Reddy ; Richard G. Cliff, Programmable logic device having embedded dual-port random access memory configurable as single-port memory.
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  319. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
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  320. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
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  326. Trimberger, Stephen M., Programmable logic device with time-multiplexed interconnect.
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  330. Snyder, Warren, Programmable microcontroller architecture.
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  335. Iadanza Joseph Andrew, Programmable read ports and write ports for I/O buses in a field programmable memory array.
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  336. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.
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  402. Teig, Steven, System in package with heat sink.
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  422. Hutchings,Brad; Redgrave,Jason, Transport network for a configurable IC.
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  423. Hutchings, Brad; Redgrave, Jason; Huang, Dai; Teig, Steven, Trigger circuits and event counters for an IC.
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  427. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
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  428. Redgrave, Jason, User registers implemented with routing circuits in a configurable IC.
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  433. Schmit,Herman; Teig,Steven, VPA logic circuits.
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  434. Hutchings, Brad, Variable width management for a memory of a configurable IC.
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  435. Hutchings, Brad, Variable width writing to a memory of an IC.
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  441. Schmit, Herman; Teig, Steven, Via programmable gate array with offset direct connections.
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