이 특허를 인용한 특허 (88)

1. Kengo Azegami JP; Koichi Yamashita JP, Chain-connected shift register and programmable logic circuit whose logic function is changeable in real time.

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2. Iwanczuk Roman ; Young Steven P. ; Schultz David P., Circuits and methods for operating a multiplexer array.

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3. Hansen, Craig; Moussouris, John; Massalin, Alexia, Computer system for executing switch and table translate instructions requiring wide operands.

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4. Hosticka Bedrich (Duisburg DEX) Schardein Werner (Kamp-Lintfort DEX) Weghaus Berthold (Dinslaken DEX), Configurable analog and digital array.

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5. Trimberger Stephen M., Configurable electronic device which is compatible with a configuration bitstream of a prior generation configurable ele.

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6. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Configuration bus interface circuit for FPGAS.

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7. David P. Schultz ; Lawrence C. Hung ; F. Erich Goetting, Configuration bus interface circuit for FPGAs.

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8. Choe, Kok Heng, Configuring a programmable logic device using a configuration bit stream without phantom bits.

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9. Choe, Kok Heng, Configuring a programmable logic device using a configuration bit stream without phantom bits.

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10. Tan, Jun Pin; Jong, Kiun Kiet, Configuring data registers to program a programmable device with a configuration bit stream without phantom bits.

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11. Rotem Eran,ILX ; Yoeli Uzi,ILX ; Phillips Richard Stephen,CAX, Customizable integrated circuit device.

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12. Krumel, Andrew K., Data protection system selectively altering an end portion of packets based on incomplete determination of whether a packet is valid or invalid.

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13. Huggins Alan H. ; Schmulian David E. ; MacPherson John ; Devanney William L., Designing integrated circuit gate arrays using programmable logic device bitstreams.

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14. Wirtz, II, Frank C.; Hubbard, John R.; Seltzer, Jeffrey H.; Shimanek, Schuyler E., Embedded function units with decoding.

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15. Wong, Wayne, Encryption for a stream file in an FPGA integrated circuit.

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16. Beal Samuel W. ; Kaptonoglu Sinan ; Lien Jung-Cheun ; Shu William ; Chan King W. ; Plants William C., Enhanced field programmable gate array.

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17. Lewis, David; Betz, Vaughn, Error correction for programmable logic integrated circuits.

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18. Lewis,David; Betz,Vaughn, Error correction for programmable logic integrated circuits.

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19. Ngo, Ninh D.; Lee, Andy L.; Veenstra, Kerry, Error detection on programmable logic resources.

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20. Ngo, Ninh D.; Lee, Andy L.; Veenstra, Kerry, Error detection on programmable logic resources.

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21. Ngo,Ninh D.; Lee,Andy L.; Veenstra,Kerry, Error detection on programmable logic resources.

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22. Iwanczuk Roman ; Young Steven P., FPGA configurable by two types of bitstreams.

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23. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, FPGA configuration circuit including bus-based CRC register.

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24. Trimberger,Stephen M., FPGA configuration memory with built-in error correction mechanism.

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25. Iwanczuk Roman ; Young Steven P. ; Schultz David P., FPGA having fast configuration memory data readback.

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26. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA logic cell internal structure including pair of look-up tables.

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27. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.

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28. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector reset lines.

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29. Goel,Ashish Kumar; Aggarwal,Davinder, FPGA-based digital circuit for reducing readback time.

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30. Mahoney John E. (San Jose CA) Trimberger Stephen M. (San Jose CA) Erickson Charles R. (Fremont CA), Fast pipeline frame full detector.

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31. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.

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32. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.

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33. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.

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34. McGowan John E., Field programmable gate array with mask programmed input and output buffers.

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35. Marshall Alan,GBX ; Stansfield Anthony,GBX ; Vuillemin Jean,FRX, Field programmable processor arrays.

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36. Marshall Alan,GBX ; Stansfield Anthony,GBX ; Vuillemin Jean,FRX, Field programmable processor devices.

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37. Mathewson,Bruce James; Harris,Antony John; Patel,Dipesh Ishwerbhai, Flexibility of use of a data processing apparatus.

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38. Mazahreh, Raied N.; Tarn, Hai-Jo; Tunali, Nihat E.; Dick, Christopher H., Hybrid architecture for LDPC channel coding in data center.

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39. Marshall, Alan David; Stansfield, Anthony; Vuillemin, Jean, Implementation of multipliers in programmable arrays.

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40. Zeng, Michelle E.; Kumar, Subodh; Durairajan, Uma; Lu, Weiguang; Rajasekharan, Karthy; Rahul, Kumar, Implementing robust readback capture in a programmable integrated circuit.

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41. He, Lei; Lee, Ju-Yueh; Feng, Zhe; Jing, Naifeng, In-place resynthesis and remapping techniques for soft error mitigation in FPGA.

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42. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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43. Laramie Michael J., Interconnect structure between heterogeneous core regions in a programmable array.

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44. Lane Christopher F. ; Reddy Srinivas T. ; Wang Bonnie I-Keh, Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices.

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45. Stansfield, Anthony; Marshall, Alan David; Vuillemin, Jean, Method and apparatus for providing instruction streams to a processing device.

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46. Stansfield, Anthony; Marshall, Alan David; Vuillemin, Jean, Method and apparatus for varying instruction streams provided to a processing device using masks.

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47. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Method and structure for configuring FPGAS.

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48. Schultz David P. ; Young Steven P. ; Hung Lawrence C., Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA.

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49. Merchant, James Daniel; Carskadon, Gordon; Evans, Brian P.; Hunt, Jeffery Scott; Nayak, Anup; Wright, Andrew, Method and system for generating a bit order data structure of configuration bits from a schematic hierarchy.

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50. Aldebert Jeane-Paul,FRX ; Basso Claude,FRX ; Calvignac Jean,FRX ; Chemla Paul,FRX ; Orsatti Daniel,FRX ; Verplanken Fabrice,FRX ; Zunino Jean-Claude,FRX, Method and system for in-site and on-line reprogramming of hardware logics with remote loading in a network device.

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51. Gill John W. ; Johnson Bruce A., Method and system of decoding compressed image data.

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52. Steven P. Young ; Jeffrey V. Lindholm, Method for compressing an FPGA bitsream.

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53. Lawman Gary R., Method for generating a secure macro element of a design for a programmable IC.

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54. Kelem, Steven H., Method of compressing a bitstream of an FPGA.

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55. Haight,Charles Francis, Method of implementing a high-speed header bypass function.

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56. Krumel,Andrew K., Methods for packet filtering including packet invalidation if packet validity determination not timely made.

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57. Krumel, Andrew K., Methods for updating the configuration of a programmable packet filtering device including a determination as to whether a packet is to be junked.

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58. Iwanczuk Roman ; Young Steven P. ; Schultz David P., Multiplexer array with shifted input traces.

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59. R챕blewski,Fr챕d챕ric, On circuit finalization of configuration data in a reconfigurable circuit.

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60. Krumel,Andrew K., PLD-based packet filtering methods with PLD configuration data update of filtering rules.

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61. Hansen, Craig; Moussouris, John; Massalin, Alexia, Processor architecture for executing wide transform slice instructions.

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62. Hansen, Craig; Moussouris, John; Massalin, Alexia, Processor architecture for executing wide transform slice instructions.

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63. Hansen, Craig; Moussouris, John; Massalin, Alexia, Processor for executing multiply matrix instructions requiring wide operands.

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64. Hansen, Craig; Moussouris, John; Massalin, Alexia, Processor for executing wide operand operations using a control register and a results register.

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65. Hansen, Craig; Moussouris, John; Massalin, Alexia, Processor for executing wide operand operations using a control register and a results register.

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66. Hansen, Craig; Moussouris, John; Massalin, Alexia, Processor for performing operations with two wide operands.

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67. Ong Randy T. ; Young Edel M., Programmable address decoder for programmable logic device.

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68. Reddy Srinivas T. ; Mejia Manuel ; Lee Andy L. ; Pedersen Bruce B., Programmable logic device with redundant circuitry.

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69. Srinivas T. Reddy ; Manuel Mejia ; Andy L. Lee ; Bruce B. Pedersen, Programmable logic device with redundant circuitry.

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70. Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.

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71. McClintock Cameron ; Lee Andy L. ; Cliff Richard G., Redundancy circuitry for logic circuits.

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72. McClintock Cameron ; Lee Andy L. ; Cliff Richard G., Redundancy circuitry for logic circuits.

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73. McClintock Cameron ; Lee Andy L. ; Cliff Richard G., Redundancy circuitry for logic circuits.

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74. David E. Jefferson ; Srinivas T. Reddy, Redundancy circuitry for programmable logic devices with interleaved input circuits.

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75. Jefferson David E. ; Reddy Srinivas T., Redundancy circuitry for programmable logic devices with interleaved input circuits.

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76. Jefferson David E. ; Reddy Srinivas T., Redundancy circuitry for programmable logic devices with interleaved input circuits.

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77. Young,Jay T.; Lindholm,Jeffrey V.; McEwen,Ian L., Routing with frame awareness to minimize device programming time and test cost.

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78. Ecker Wolfgang,DEX, Signal propagation time optimization method for reprogrammable circuit that arranges same number of combinator blocks between each two utilized registers on programmed series.

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79. Parekh, Umang; Sundararajan, Arvind; Dutta, Sandeep, Simulation of system designs.

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80. Iwanczuk Roman ; Young Steven P., Structure and method for loading narrow frames of data from a wide input bus.

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81. Iwanczuk Roman ; Young Steven P., Structure and method for loading wide frames of data from a narrow input bus.

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82. Hansen, Craig; Moussouris, John; Massalin, Alexia, System and methods for expandably wide processor instructions.

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83. Hansen, Craig; Moussouris, John; Massalin, Alexia, System and methods for expandably wide processor instructions.

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84. Cliff Richard G. ; Reddy Srinivas T. ; Papaliolios Andreas, Techniques for programming programmable logic array devices.

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85. Cliff Richard G. ; Reddy Srinivas T. ; Veenstra Kerry ; Papaliolios Andreas ; Sung Chiakang ; Terrill Richard Shaw ; Raman Rina ; Bielby Robert Richard Noel, Techniques for programming programmable logic array devices.

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86. Richard G. Cliff ; Srinivas T. Reddy ; Kerry Veenstra ; Andreas Papaliolios ; Chiakang Sung ; Richard Shaw Terrill ; Rina Raman ; Robert Richard Noel Bielby, Techniques for programming programmable logic array devices.

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87. Veenstra Kerry (San Jose CA) Bielby Robert Richard Noel (Pleasonton CA), Techniques for programming programmable logic array devices.

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88. Hopkins, Jeremy T.; Rosser, Thomas E., Techniques for selecting spares to implement a design change in an integrated circuit.

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