이 특허를 인용한 특허 (37)

1. Ko, Bok Rim; Kim, Keun Kook, Command generation circuit and semiconductor memory device.

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2. Ko, Bok Rim; Kim, Keun Kook, Command generation circuit and semiconductor memory device.

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3. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.

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4. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.

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5. Douglass, Stephen M.; Ansari, Ahmad R., Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor.

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6. Downs Jeffery E., Data processor incorporating a ferroelectric memory array selectably configurable as read/write and read only memory.

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7. Mann Shari L. ; Pena David J. A. ; Studor Charles F. ; McKinnon Gordon W.,GBX, Data processor with transparent operation during a background mode and method therefor.

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8. Rupp, Charle' R.; Garverick, Timothy L.; Arnold, Jeffrey, Design methodology for merging programmable logic into a custom IC.

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9. Ishii Shuichi,JPX, Disk system with command processing function.

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10. Paul A. Santeler ; Kenneth A. Jansen ; Sompong P. Olarig, Fault tolerant memory.

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11. Santeler Paul A. ; Jansen Kenneth A. ; Olarig Sompong P., Fault tolerant memory.

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12. Basset Philippe,FRX, Integrated circuit comprising a microprocessor, a memory and internal configurable peripherals.

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13. Santeler,Paul A.; Jansen,Kenneth A.; Olarig,Sompong P., Main memory controller adapted to correct corrupted data by xoring corrupted data to directly generate correct data.

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14. Coulman, Paula Kristine; Dhong, Sang Hoo; Flachs, Brian King; Hofstee, Harm Peter; Park, Jaehong; Posluszny, Stephen Douglas; Silberman, Joel Abraham; Takahashi, Osamu, Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays.

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15. Eickemeyer Richard James ; Johnson Ross Evan ; Kossman Harold F. ; Kunkel Steven Raymond ; Mullins Timothy John ; Rose James Allen, Method and system for multi-thread switching only when a cache miss occurs at a second or higher level.

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16. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.

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17. Moore, Michael T., Method of programming PLDs using a wireless link.

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18. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.

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19. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.

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20. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.

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21. Kawasaki Shumpei,JPX ; Akao Yasushi,JPX ; Noguchi Kouki,JPX ; Hasegawa Atsushi,JPX ; Ohsuga Hiroshi,JPX ; Kurakazu Keiichi,JPX ; Matsubara Kiyoshi,JPX ; Hayakawa Akio,JPX ; Ito Yoshitaka,JPX, Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller.

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22. Mann,Eric N., Microcontroller with programmable logic.

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23. Mann, Eric N., Microcontroller with programmable logic on a single chip.

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24. Long, Timothy Merrick; Gibson, Ian; Amies, Christopher, Multi-instruction stream processor.

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25. Cetin, Joseph A.; Sienko, Matthew D., Operational amplifier and method for amplifying a signal with shared compensation components.

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26. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.

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27. Kawasaki, Shumpei; Akao, Yasushi; Noguchi, Kouki; Hasegawa, Atsushi; Ohsuga, Hiroshi; Kurakazu, Keiichi; Matsubara, Kiyoshi; Hayakawa, Akio; Ito, Yoshitaka, Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals.

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28. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.

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29. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.

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30. Nishitani, Shuji, Programmable microcontroller for controlling multichannel sequences of states to be processed in each processing period.

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31. Kawasaki Shumpei,JPX ; Akao Yasushi,JPX ; Noguchi Kouki,JPX ; Hasegawa Atsushi,JPX ; Ohsuga Hiroshi,JPX ; Kurakazu Keiichi,JPX ; Matsubara Kiyoshi,JPX ; Hayakawa Akio,JPX ; Ito Yoshitaka,JPX, Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals.

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32. Kawasaki Shumpei,JPX ; Akao Yasushi,JPX ; Noguchi Kouki,JPX ; Hasegawa Atsushi,JPX ; Ohsuga Hiroshi,JPX ; Kurakazu Keiichi,JPX ; Matsubara Kiyoshi,JPX ; Hayakawa Akio,JPX ; Ito Yoshitaka,JPX, Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal.

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33. Kawasaki, Shumpei; Akao, Yasushi; Noguchi, Kouki; Hasegawa, Atsushi; Ohsuga, Hiroshi; Kurakazu, Keiichi; Matsubara, Kiyoshi; Hayakawa, Akio; Ito, Yoshitaka, Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements.

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34. Kawasaki, Shumpei; Akao, Yasushi; Noguchi, Kouki; Hasegawa, Atsushi; Ohsuga, Hiroshi; Kurakazu, Keiichi; Matsubara, Kiyoshi; Hayakawa, Akio; Ito, Yoshitaka, Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory.

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35. Sundararajarao Mohan ; Stephen M. Trimberger, System and method of computation in a programmable logic device using virtual instructions.

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36. Tran Nghia ; Li Ying Xuan ; Balicki Janusz ; Costello John, System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to m.

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37. Tran,Nghia; Li,Ying Xuan; Balicki,Janusz; Costello,John, System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly.

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