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Distributed memory architecture for a configurable logic array and method for using distribution memory 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/003
출원번호 US-0284935 (1994-08-01)
발명자 / 주소
  • Freeman Ross H. (San Jose CA) Hsieh Hung-Cheng (Sunnyvale CA)
출원인 / 주소
  • Xilinx, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 71  인용 특허 : 0

초록

This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other p

대표청구항

In a field programmable logic device having a programmable interconnect structure and a plurality of logic blocks, each logic block comprising at least one lookup table having memory cells which can be loaded from a bitstream during configuration of said field programmable logic device and loaded fr

이 특허를 인용한 특허 (71)

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  3. New, Bernard J.; Wittig, Ralph D.; Mohan, Sundararajarao, Configurable logic element with expander structures.
  4. New, Bernard J.; Wittig, Ralph D.; Mohan, Sundararajarao, Configurable logic element with expander structures.
  5. New,Bernard J.; Wittig,Ralph D.; Mohan,Sundararajarao, Configurable logic element with expander structures.
  6. New,Bernard J.; Wittig,Ralph D.; Mohan,Sundararajarao, Configurable logic element with expander structures.
  7. Ralph D. Wittig ; Sundararajarao Mohan ; Bernard J. New, Configurable lookup table for programmable logic devices.
  8. Andy L. Lee ; Christopher F. Lane ; Srinivas T. Reddy ; Brian D. Johnson ; Ketan H. Zaveri ; Mario Guzman ; Quyen Doan, Configurable memory structures in a programmable logic device.
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  11. Flaherty, Edward; Dickinson, Mark, Configuration and/or reconfiguration of integrated circuit devices that include programmable logic and microprocessor circuitry.
  12. Flaherty,Edward; Dickinson,Mark, Configuration and/or reconfiguration of integrated circuit devices that include programmable logic and microprocessor circuitry.
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  14. Guzman,Mario; Lane,Chris; Lee,Andy L.; Ngo,Ninh, Configuration shift register.
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  18. Or-Bach Zvi ; Wurman Ze'ev ; Zeman Richard ; Cooke Laurance, Customizable and programmable cell array.
  19. Or-Bach, Zvi, Customizable and programmable cell array.
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  24. Lewis,David; Leventis,Paul; Betz,Vaughn, Distributed random access memory in a programmable logic device.
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  28. Lysaght, Patrick, Exploiting unused configuration memory cells.
  29. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
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  40. Reddy Srinivas T. ; Gupta Anil, Look-up table using multi-level decode.
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  55. Ikeda, Takayuki; Kurokawa, Yoshiyuki, Programmable logic device and semiconductor device.
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  59. Jung, Chulmin; Setiadi, Dadi; Kim, YoungPil; Liu, Harry Hongyue; Lee, Hyung-Kyu, Semiconductor control line address decoding circuit.
  60. Jung, Chulmin; Setiadi, Dadi; Kim, YoungPil; Liu, Harry Hongyue; Lee, Hyung-Kyu, Semiconductor control line address decoding circuit.
  61. Bjorklund, Nora; Aoki, Takeshi; Kurokawa, Yoshiyuki, Semiconductor device.
  62. Ikeda, Takayuki; Kurokawa, Yoshiyuki, Semiconductor device.
  63. Lee, Andy L.; Johnson, Brian; Cliff, Richard G., Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter.
  64. Leedy, Glenn J, Three dimension structure memory.
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