[특허]Power control technique for a computer system to provide adjustable storage and non-storage access times and an adjustab

Power control technique for a computer system to provide adjustable storage and non-storage access times and an adjustab 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-013/10
출원번호	US-0066303 (1993-05-21)
우선권정보	JP-0130807 (1992-05-22)
발명자 / 주소	Doi Katsuo (Sakurai JPX)
출원인 / 주소	Sharp Kabushiki Kaisha (Osaka JPX 03)
인용정보	피인용 횟수 : 21 인용 특허 : 0

초록 ▼

A power control apparatus having a plurality of external devices and adapted to be used for a computer system and to reduce the power consumption in an idle state, the apparatus includes a processing unit for receiving a signal from at least one of the plurality of external devices and for outputting an instruction according to the received signal, a storage unit connected to the processing unit for temporary storing information and for accessing to the processing unit according to the instruction output from the processing unit, an interface unit connected to both the processing unit and the storage unit for controlling an interface between the processing unit and the storage unit, and an adjusting unit connected to the interface unit for adjusting a time proportion of an access cycle to a non-storage unit, for adjusting a time proportion in an operation of the processing unit to be stopped, and for adjusting an access to the storage unit.

대표청구항 ▼

A power control apparatus having a plurality of external devices and used for a computer system and to reduce the power consumption in an idle state, the apparatus comprising: processing means for receiving a signal from at least one of said plurality of external devices and for outputting an instruction according to said received signal; storage means connected to said processing means for temporarily storing information and for accessing to said processing means according to said instruction output from said processing means; interface means connected to both said processing means and said storage means for controlling an interface between said processing means and said storage means; and adjusting means connected to said interface means for adjusting the time proportion of an access cycle for said storage means to an access cycle for a non-storage means and for adjusting the time period during which the processor should be idle, wherein each of said plurality of external devices includes an input/output device, a main memory, a read-only memory, and at least two peripheral devices, said adjusting means including an acknowledge generating circuit connected to said interface means for generating an acknowledge signal during a predetermined time period so as to terminate an access cycle of one of said peripheral devices.

이 특허를 인용한 특허 (21)

Fan, Xiaobo; Hennecke, Mark D.; Heath, Taliver Brooks, Accurate power allotment.
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Evoy David R. (Tempe AZ), Apparatus for monitoring distributed I/O device by providing a monitor in each I/O device control for generating signals.
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Ramsey Jens K. ; Stevens Jeffrey C. ; Tubbs Michael E. ; Stancil Charles J., Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Computer and data center load determination.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage.
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Shibuya, Noboru; Agata, Kenichi; Miyano, Akihiro, General-purpose computer and copyright management method for use therein.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Load control in a data center.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Load control in a data center.
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Maiyuran, Subramaniam J.; Moulton, Lyman, Low power cache architecture.
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Maiyuran,Subramaniam J.; Moulton,Lyman; Palanca,Salvador; Damaraju,Satish, Low power cache architecture.
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Nishiyama Hiroyasu,JPX ; Kikuchi Sumio,JPX ; Mori Noriyasu,JPX ; Nishimoto Akira,JPX ; Takeuchi Yooichi,JPX, Method for controlling a processor for power-saving in a computer for executing a program, compiler medium and processo.
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Fan, Xiaobo; Hennecke, Mark D.; Heath, Taliver Brooks, Method of correlating power in a data center by fitting a function to a plurality of pairs of actual power draw values and estimated power draw values determined from monitored CPU utilization of a statistical sample of computers in the data center.
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Rakvic,Ryan N.; Shen,John P.; Limaye,Deepak, Parallel cachelets.
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Rakvic,Ryan N.; Shen,John P.; Limaye,Deepak, Parallel cachelets.
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Weber, Wolf-Dietrich; Fan, Xiaobo; Barroso, Luiz Andre, Powering a data center.
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Hoshina,Shoji; Isomura,Masakazu; Todoroki,Akinari, Processor control device for stopping processor operation.
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Fuller Samuel (Austin TX), Secondary cache system for portable computer.
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Talkin, David; Brooks, Alec, Supplying grid ancillary services using controllable loads.
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Gephardt Douglas D. ; Horton Kelly M., System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Power control technique for a computer system to provide adjustable storage and non-storage access times and an adjustab 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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연합인증

Power control technique for a computer system to provide adjustable storage and non-storage access times and an adjustab 원문보기

초록 ▼

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연구과제 타임라인

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이 특허를 인용한 특허 (21)

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