[특허]Method for manufacturing semiconductor integrated circuit device having a fuse element

Method for manufacturing semiconductor integrated circuit device having a fuse element 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/70 H01L-027/00
출원번호	US-0278073 (1994-07-20)
우선권정보	JP-0178676 (1993-07-20)
발명자 / 주소	Yoshizumi Keiichi (Kokubunji JPX) Fukuda Kazushi (Kodaira JPX) Ariga Seiichi (Ohme JPX) Ikeda Shuji (Koganei JPX) Saeki Makoto (Ohme JPX) Nagai Kiyoshi (Kodaira JPX) Hashiba Soichiro (Nagoya JPX) Nis
출원인 / 주소	Hitachi, Ltd. (Tokyo JPX 03) Hitachi ULSI Engineering Corp. (Tokyo JPX 03)
인용정보	피인용 횟수 : 52 인용 특허 : 0

초록 ▼

In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.

대표청구항 ▼

A method for manufacturing a semiconductor integrated circuit device, comprising steps of: (a) providing a semiconductor substrate having a main surface, with a fuse element on said main surface; (b) forming an interlayer insulating film over said fuse element so as to cover said fuse element and said main surface; (c) forming a wiring line having a bonding pad forming region on said interlayer insulating film; (d) forming a first insulating film on said wiring line and said interlayer insulating film so as to cover said main surface; (e) selectively removing said first insulating film on said bonding pad forming region by etching; (f) forming a second insulating film on said bonding pad forming region and said first insulating film so as to cover said main surface; (g) selectively removing said second insulating film on said bonding pad forming region and said fuse element so as to expose said bonding pad forming region of said wiring line and so as to form an aperture over said fuse element by etching; (h) conducting an electrical test while applying a probe to said bonding pad forming region; and (i) cutting the fuse element under said aperture in accordance with the results of said electrical test.

이 특허를 인용한 특허 (52)

Stamper Anthony K., Closely pitched polysilicon fuses and method of forming the same.
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Stamper Anthony K., Closely pitched polysilicon fuses and method of forming the same.
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Liaw Jhon-Jhy,TWX, Fuse window guard ring structure for nitride capped self aligned contact processes.
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Lee Pei-Ing Paul ; Klaasen William Alan ; Mitwalsky Alexander, Fuse window with controlled fuse oxide thickness.
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Huang Ji-Chung,TWX ; Hsieh Jang-Cheng,TWX ; Wu Chung-Cheng,TWX ; Huang Kuo-Ching,TWX, Hydrogen thermal annealing method for stabilizing microelectronic devices.
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Chevallier Christophe J., Integrated circuit probe pad metal level.
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Bowen, Carl L.; Lao, Keith Q., Method for forming an integrated circuit having a bonding pad and a fuse.
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Choi,Ja Young; Lee,Ki Young, Method for forming fuse integrated with dual damascene process.
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Yaung Dun-Nian,TWX ; Wuu Shou-Gwo,TWX ; Lee Jin-Yuan,TWX ; Chin Hsien Wei,TWX, Method of forming a moisture guard ring for integrated circuit applications.
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Stamper Anthony K., Method of forming closely pitched polysilicon fuses.
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Lee,Jun Seok, Methods of fabricating semiconductor devices.
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Chen Chung-zen (Hsinchu TWX), Moisture guard ring for integrated circuit applications.
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Hui, Frank Y.; Harris, Edward B., Preweakened on chip metal fuse using dielectric trenches for barrier layer isolation.
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Manley Martin, Programmable fuse and method therefor.
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Lou Yung-Song,TWX ; Rou Ching-Cherng,TWX ; Chou Ting,TWX ; Koh Chao-Ming,TWX ; Lee Shin-Chi,TWX ; Chen Chuen-Nan,TWX, Raised fuse structure for laser repair.
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Appel, Andrew T., Rectangular contact used as a low voltage fuse element.
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Appel, Andrew T., Rectangular contact used as a low voltage fuse element.
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Appel,Andrew T., Rectangular contact used as a low voltage fuse element.
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Gary K. Giust ; Ruggero Castagnetti ; Yauh-Ching Liu ; Subramanian Ramesh, Self-aligned fuse structure and method with dual-thickness dielectric.
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Giust Gary K. ; Castagnetti Ruggero ; Liu Yauh-Ching ; Ramesh Subramanian, Self-aligned fuse structure and method with heat sink.
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Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
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Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads.
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Song, Young-Hee; Choi, Il-Heung; Kim, Jeong-Jin; Sohn, Hae-Jeong; Lee, Chung-Woo, Semiconductor chip having bond pads.
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Song,Young Hee; Choi,Il Heung; Kim,Jeong Jin; Sohn,Hae Jeong; Lee,Chung Woo, Semiconductor chip having bond pads.
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Song, Young Hee; Choi, Il Heung; Kim, Jeong Jin; Sohn, Hae Jeong; Lee, Chung Woo, Semiconductor chip having bond pads and multi-chip package.
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Nagano Yoshihisa,JPX ; Kutsunai Toshie,JPX ; Judai Yuji,JPX ; Uemoto Yasuhiro,JPX ; Fujii Eiji,JPX, Semiconductor device and method for fabricating the same.
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Nagano, Yoshihisa; Kutsunai, Toshie; Judai, Yuji; Uemoto, Yasuhiro; Fujii, Eiji, Semiconductor device and method for fabricating the same.
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Kim, Byung yoon; Lee, Won seong; Park, Young woo, Semiconductor device capable of preventing moisture-absorption of fuse area thereof and method for manufacturing the fuse area.
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Nishimura Yasumasa,JPX ; Ito Keiko,JPX ; Takeoka Hiroyuki,JPX ; Maruta Masanao,JPX ; Moriyasu Masaharu,JPX, Semiconductor device having a fuse layer.
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Shiratake Shigeru,JPX ; Genjo Hideki,JPX ; Ido Yasuhiro,JPX ; Hachisuka Atsushi,JPX ; Taniguchi Koji,JPX, Semiconductor device having a metallic fuse member and cutting method thereof with laser light.
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Seung-Jae Lee KR; Tae-Wook Seo KR; Sun-Hoo Park KR, Semiconductor integrated circuit device and method of manufacturing the same.
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Narayan Chandrasekhar ; Dinkel Bettina, Soft passivation layer in semiconductor fabrication.
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Lee,Ki Am; Kwon,Sang Deok; Lee,Jong Hyun, Structure and method for failure analysis in a semiconductor device.
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Bold, Thomas, System and apparatus that reduce corrosion of an integrated circuit through its bond pads.
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Bold, Thomas, System and method for reducing corrosion of an integrated circuit through its bond pads.
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Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Method for manufacturing semiconductor integrated circuit device having a fuse element 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

이 특허를 인용한 특허 (52)

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연합인증

Method for manufacturing semiconductor integrated circuit device having a fuse element 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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이 특허를 인용한 특허 (52)

관련 콘텐츠

특허 원문 보기

IPC 상위 출원인

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