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Electrical interconnection substrate with both wire bond and solder contacts, and fabrication method 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B23K-031/00
  • H01L-021/02
출원번호 US-0324271 (1994-10-13)
발명자 / 주소
  • Trask Philip A. (Laguna Hills CA) Pillai Vincent A. (Irvine CA) Gierhart Thomas J. (Fountain Valley CA)
출원인 / 주소
  • Hughes Aircraft Company (Los Angeles CA 02)
인용정보 피인용 횟수 : 28  인용 특허 : 0

초록

An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. T

대표청구항

A method of preparing an electrical interconnection substrate to receive electrical circuit elements by both wire bonded and soldered connections, the substrate having a plurality of wire bond contact pads formed with a layer of conductive wire bonding material, comprising: forming a solder mask ove

이 특허를 인용한 특허 (28)

  1. Kuah, BengKit; Lee, Lucas KongYaw; Rugg, William L.; Yuen, SaiPo; Koh, William B S; Tan, Jui Whatt, Assessing connection joint coverage between a device and a printed circuit board.
  2. Lin Kwang-Lung,TWX ; Yu Chih-Mei,TWX ; Chao Wen-Hsiuan,TWX, Continuous process for producing solder bumps on electrodes of semiconductor chips.
  3. Fauty Joseph K. ; Letterman ; Jr. James P. ; Seddon Michael J., Electronic component and method of manufacture.
  4. Tain Alexander C., Integrated circuit package verification.
  5. Corisis David J., Leads under chip IC package.
  6. Corisis, David J., Leads under chip IC package.
  7. Corisis,David J., Leads under chip IC package.
  8. Corisis David J., Leads under chip in conventional IC package.
  9. Corisis David J., Leads under chip in conventional IC package.
  10. Corisis David J., Leads under chip in conventional IC package.
  11. David J. Corisis, Leads under chip in conventional IC package.
  12. Farnworth, Warren M., Method for fabricating semiconductor components with conductors having wire bondable metalization layers.
  13. Pierson, Mark Vincent, Method for forming solder connections on a circuitized substrate.
  14. Rajagopalan, Sarathy; Desai, Kishor, Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die.
  15. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
  16. Ho, Kwok Keung Paul; Chooi, Simon; Xu, Yi; Aliyu, Yakub; Zhou, Mei Sheng; Sudijono, John Leonard; Gupta, Subhash; Roy, Sudipto Ranendra, Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding.
  17. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Mei Sheng Zhou SG; Yakub Aliyu SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of copper solution in flip-chip, COB, and micrometal bonding.
  18. Corisis, David J., Methods for leads under chip in conventional IC package.
  19. Furuta, Toru; Takagi, Kotaro; Ido, Michio; Miyata, Akihiro; Takagi, Fumitaka, Printed wiring board.
  20. Wakefield,Elwyn Paul Michael, Process for forming electrical/mechanical connections.
  21. Patrick W. Tandy, Selectively coating bond pads.
  22. Farnworth, Warren M., Semiconductor component having conductors with wire bondable metalization layers.
  23. Farnworth,Warren M., Semiconductor component having conductors with wire bondable metalization layers.
  24. Haga, Motoharu; Kasuya, Yasumasa; Matsubara, Hiroaki, Semiconductor device, production method for the same, and substrate.
  25. Heng, Mung Suan; Tan, Kok Chua; Leong, Vince Chan Seng; Johnson, Mark S., Stacked microfeature devices and associated methods.
  26. Yang, Chih-kuang; Hsing, Chieh-lin, Surface finish structure of multi-layer substrate and manufacturing method thereof.
  27. Hsu, Chien-En; Liang, Chih-Nan; Lee, Po-Sheng, Wet cleaning process and method for fabricating semiconductor device using the same.
  28. Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Wire and solder bond forming methods.
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