초록 ▼

The present invention provides an apparatus for detecting whether a program having an iterative loop can be processed in parallel. The apparatus includes including a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing values of variables that

The present invention provides an apparatus for detecting whether a program having an iterative loop can be processed in parallel. The apparatus includes including a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing values of variables that are defined by program statements executed during simulation of the iterations, each stored variable being stored with information showing a location in the program where the value of the variable is defined and the simulated iteration number during which the variable is defined, and a judgement unit for judging that parallel processing is possible when, for each simulated iteration, variables appearing undefined in any program statements of that iteration are defined in preceding program statements within that iteration. The present invention further provides a program translation apparatus for generating a program applicable to parallel processing if a possibility of executing the program in parallel is detected. The program translation apparatus includes the simulation unit, the variable storage unit, the judgement unit, and program generation circuitry for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

대표청구항 ▼

An apparatus for detecting whether iterations of a program loop can be processed in parallel, comprising: simulation means for simulating each iteration of the program loop comprising: a variable detector for one side for detecting variables on one side of assignment statements during each simulated

An apparatus for detecting whether iterations of a program loop can be processed in parallel, comprising: simulation means for simulating each iteration of the program loop comprising: a variable detector for one side for detecting variables on one side of assignment statements during each simulated iteration as the defined variables; an iteration identification means for identifying the numbers of the simulated iterations in which each defined variable is defined; and registration means for registering to the variable storage means information on each defined variable detected by the variable detector along with information on the number of the simulated iteration identified by the iteration identification means; variable storage means for storing values of variables, which are defined in program statements executed during simulation of the iterations, each value being stored with information showing both a location in the program where the value of the variable is defined and a number of the simulated iteration in which the variable is defined; and judgement means for judging that parallel processing is possible when, for each simulated iteration, variables appearing undefined in any program statements of that iteration are defined in preceding program statements within that iteration.