[특허]Unified floating point and integer datapath for a RISC processor

Unified floating point and integer datapath for a RISC processor 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/00
출원번호	US-0063183 (1993-05-17)
발명자 / 주소	Kowalczyk Andre (San Jose CA) Yeung Norman K. P. (Fremont CA)
출원인 / 주소	MIPS Technologies Inc. (Mountain View CA 02)
인용정보	피인용 횟수 : 54 인용 특허 : 0

초록 ▼

A 64-bit wide unified integer and floating-point datapath for a RISC processor. The unified datapath allows for the sharing of some of the major hardware resources within the integer and floating-point execution units, as well as simplifying a large portion of the peripheral circuitry. The unified datapath results in a more efficient use of the hardware with reduced average power dissipation and area, without compromising the major performance advantages of RISC processors.

대표청구항 ▼

In a reduced instruction set computer (RISC) processor having a multi-stage pipelined datapath, a unified integer and floating-point datapath comprising: a register file combining a plurality of general purpose registers and a plurality of floating-point registers; an integer/mantissa execution unit, coupled to said register file, said integer/mantissa execution unit comprising: an adder, a shifter, a Boolean logic functional unit, a normalization logic unit, and a multiplexing network selectively routing operands to said adder, shifter, Boolean logic functional unit and normalization logic unit, an exponent execution unit coupled to said register file; and a unified control unit incorporating a superset of integer and floating-point instructions, said unified control unit coupled to said integer/mantissa execution unit and said exponent execution unit for controlling the operation and flow of operands through said integer/mantissa and exponent execution units, wherein said multiplexing network in said integer/mantissa execution unit comprises: a plurality of shift multiplexers having inputs coupled to receive operands, and having control inputs coupled to said unified control unit; a booth multiplexer having inputs coupled to outputs of said shift multiplexers, and an output coupled to a first input of said adder; an add multiplexer having inputs coupled to outputs of said shift multiplexers, and an output coupled to second input of said adder; a first multiplexer having inputs coupled to an output of said shifter and an output of said Boolean logic functional unit, respectively, a control input coupled to said unified control unit, and an output; a result multiplexer having a first input coupled to an output of said adder, a second input coupled to an output of said first multiplexer, and a control input coupled to said unified control unit; and a sum register for temporarily storing an output of said result multiplexer, and for feeding back said output of said result multiplexer to said shift multiplexers.

이 특허를 인용한 특허 (54)

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Unified floating point and integer datapath for a RISC processor 원문보기

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Unified floating point and integer datapath for a RISC processor 원문보기

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