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Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
출원번호 US-0162678 (1993-12-06)
발명자 / 주소
  • Ho Walford W. (Saratoga CA) Chen Chao-Chiang (Cupertino CA) Yang Yuk Y. (Foster City CA)
출원인 / 주소
  • Intelligent Logic Systems, Inc. (Saratoga CA 02)
인용정보 피인용 횟수 : 380  인용 특허 : 0

초록 ▼

A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includ

대표청구항 ▼

A hierarchically-structured programmable logic array, comprising: a plurality of sectors, each sector comprising: a plurality of logic cells; and a sector bus system for interconnecting said logic cells within said sector; a block bus system disposed externally to said sectors; and an interface for

이 특허를 인용한 특허 (380)

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  161. John E. Turner ; Rakesh H. Patel, Interface for low-voltage semiconductor devices.
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  163. Martin Vorbach DE; Robert Munch DE, Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  164. Vorbach,Martin; M체nch,Robert, Internal bus system for DFPS and units with two-or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity.
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  165. Vorbach, Martin; May, Frank; Reichardt, Dirk; Lier, Frank; Ehlers, Gerd; Nückel, Armin; Baumgarte, Volker; Rao, Prashant; Oertel, Jens, Logic cell array and bus system.
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  168. Francis B. Heile, Logic device architecture and method of operation.
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  172. Verdoorn, David Joel; Woodward, Sandra S., Method and apparatus for debugging a chip.
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  173. Bernard J. New ; Steven P. Young, Method and apparatus for incorporating a multiplier into an FPGA.
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  175. Pani Peter M. ; Ting Benjamin S., Method and apparatus for universal program controlled bus.
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  182. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  183. Vorbach, Martin; May, Frank; Nuckel, Armin, Method and device for processing data.
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  184. Vorbach, Martin; Munch, Robert, Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  185. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  186. Vorbach, Martin, Method for debugging reconfigurable architectures.
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  190. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
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  191. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  192. Maeda Sumiko,JPX ; Fukase Hisataka,JPX, Method for making electronic circuit design data and CAD system using the method.
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  193. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.
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  194. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  195. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
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  196. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  197. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  198. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.
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  199. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
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  201. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  202. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  203. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  213. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  214. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  222. Lee,Andy L.; McClintock,Cameron; Johnson,Brian; Cliff,Richard; Reddy,Srinivas; Lane,Chris; Leventis,Paul; Betz,Vaughn Timothy; Lewis,David, Methods for designing PLD architectures for flexible placement of IP function blocks.
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  223. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.
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  235. Cliff Richard G. ; Heile Francis B. ; Huang Joseph ; Mendel David W. ; Pedersen Bruce B. ; Sung Chiakang ; Veenstra Kerry ; Wang Bonnie I., PCI-compatible programmable logic devices.
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  261. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
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  263. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
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  264. Clinton Kim P. N. (Essex Junction VT) Gould Scott W. (South Burlington VT) Hartman Steven P. (Jericho VT) Iadanza Joseph A. (Hinesburg VT) Keyser ; III Frank R. (Colchester VT) Millham Eric E. (St. G, Programmable array interconnect network.
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