이 특허를 인용한 특허 (67)

1. Rostoker Michael D. (San Jose CA) Pasch Nicholas F. (Pacifica CA), Apparatus for mounting integrated circuit chips on a Mini-Board.

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2. Slupe, James P.; Harper, Timothy V.; Wiedeback, Fred R., Apparatus for routing signals.

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3. Leonard E. Mess, Ball grid array (BGA) encapsulation mold.

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4. Mess Leonard E., Ball grid array (BGA) encapsulation mold.

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5. Mess Leonard E., Ball grid array (BGA) encapsulation mold.

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6. Mess Leonard E., Ball grid array (BGA) encapsulation mold.

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7. Kirkland Janet ; Schneider Mark R., Ball grid array with inexpensive threaded secure locking mechanism to allow removal of a threaded heat sink therefrom.

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8. Moriyama Yoshifumi,JPX, Bump electrode with adjacent pad and insulation for solder flow stopping.

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9. Peter R. Ewer GB, Chip scale package.

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10. Ewer Peter R.,GBX, Chip scale packaging process.

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11. Zak Robert L., Chip-on-board printed circuit manufacturing process using aluminum wire bonded to copper pads.

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12. Nakano,Hiroaki, Circuit board for mounting a semiconductor chip and manufacturing method thereof.

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13. Akram Salman, Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications.

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14. Salman Akram, Device and method for electrically or thermally coupling to the backsides of integrated circuit dice in chip-on-board applications.

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15. James M. Wark, Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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16. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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17. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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18. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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19. Hauser, Christian; Winderl, Johann; Pohl, Jens, Device for packaging electronic components.

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20. Harper, Jr., Donald K., Electrical connector housing.

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21. Mess, Leonard E., Encapsulation method in a molding machine for an electronic device.

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22. Auch,Mark; Guenther,Ewald; Chua,Soo Jin, Encapsulation of electroluminescent devices with shaped spacers.

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23. Auch,Mark; Guenther,Ewald; Fang,Lim Shuang; Jin,Chua Soo, Encapsulation of electronic devices.

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24. Auch,Mark; Guenther,Ewald; Chua,Soo Jin, Encapsulation of electronic devices with shaped spacers.

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25. Kobayashi, Kazuhiko; Sano, Yoshiaki, High-frequency module.

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26. Carichner Karla Y. ; Liang Dexin, Interposer for ball grid array (BGA) package.

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27. Caletka, David Vincent; Darbha, Krishna; Infantolino, William; Johnson, Eric Arthur, Land grid array stiffener for use with flexible chip carriers.

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28. Caletka, David Vincent; Darbha, Krishna NMN; Infantolino, William NMN; Johnson, Eric Arthur, Land grid array stiffener use with flexible chip carriers.

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29. Sun, Ming; Gong, Demei, Low profile flip chip power module and method of making.

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30. Suzuki Katsunobu,JPX ; Suzuki Katsuhiko,JPX ; Haga Akira,JPX ; Sorimachi Isamu,JPX ; Uchida Hiroyuki,JPX, Metal base package for a semiconductor device.

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31. John Pierre McCormick ; Kishor V. Desai, Method for attaching solderballs by selectively oxidizing traces.

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32. Bruno Furbacher DE; Friedrich Lupp DE; Wolfgang Pahl DE; Gunter Trausch DE, Method for producing an encapsulation for a SAW component operating with surface acoustic waves.

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33. Pastore John R. ; Nomi Victor K. ; Wilson Howard P., Method for testing a ball grid array semiconductor device and a device for such testing.

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34. Ball,Michael B., Method of fabricating a multi-die semiconductor package assembly.

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35. Yong-Tae Kwon KR, Method of fabricating a wire arrayed chip size package.

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36. Betran Mario Federico Cespedes,MXX ; Reyes Manuel Maximiliano Haro,MXX ; Osorio Miguel Angel Lopez,MXX ; Hagelsieb Luis Moreno,MXX ; Hijar Jose de Jesus De,MXX ; Serrano Juan Rubio,MXX ; Rodrigo Juan, Method of manufacturing a semiconductor component from a conductive substrate containing a plurality of vias.

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37. Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.

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38. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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39. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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40. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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41. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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42. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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43. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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44. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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45. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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46. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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47. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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48. Stephens, Tab A.; McShane, Michael B.; Pelley, Perry H., Microelectronic assembly having a heat spreader for a plurality of die.

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49. Stephens, Tab A.; McShane, Michael B.; Pelley, Perry H., Microelectronic assembly having a heat spreader for a plurality of die.

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50. Norman Lee Owens, Multi-strand substrate for ball-grid array assemblies and method.

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51. Owen,Norman Lee, Multi-strand substrate for ball-grid array assemblies and method.

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52. Owens, Norman Lee, Multi-strand substrate for ball-grid array assemblies and method.

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53. Owens,Norman Lee, Multi-strand substrate for ball-grid array assemblies and method.

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54. Lassmann, Wilfried; Büttner, Christian, Multilayer printed circuit board and device comprising the same.

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55. Auch, Mark; Guenther, Ewald; Fang, Lim Shuang; Jin, Chua Soo; Ling, Low Bee, Organic electronic devices with an encapsulation.

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56. Shinji Ohuchi JP; Harufumi Kobayashi JP; Yasushi Shiraishi JP, Resin-encapsulated semiconductor device.

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57. Soyano Shin (Nagano JPX) Toba Susumu (Nagano JPX), Semiconductor device.

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58. Yamada Shigeru,JPX ; Uchida Yasufumi,JPX ; Murakami Noriko,JPX ; Shizuno Yoshinori,JPX, Semiconductor device having a die pad structure for preventing cracks in a molding resin.

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59. Miyawaki, Katumi, Semiconductor device having a package structure.

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60. Shigeru Yamada JP; Yasufumi Uchida JP; Noriko Murakami JP; Yoshinori Shizuno JP, Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor.

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61. Yamada, Shigeru; Uchida, Yasufumi; Murakami, Noriko; Shizuno, Yoshinori, Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same.

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62. Yamada Shigeru,JPX ; Uchida Yasufumi,JPX ; Murakami Noriko,JPX ; Shizuno Yoshinori,JPX, Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same.

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63. Yilmaz, Hamza; Sapp, Steven; Wang, Qi; Li, Minhua; Murphy, James J.; Diroll, John Robert, Semiconductor die packages using thin dies and metal substrates.

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64. Kim Jin Sung,KRX, Semiconductor package substrate and ball grid array (BGA) semiconductor package using same.

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65. Ichihashi Motomi,JPX, Semiconductor sensor with protective cap covering exposed conductive through-holes.

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66. Kinzer, Daniel M.; Arzumanyan, Aram; Sammon, Tim, Vertical conduction flip-chip device with bump contacts on single surface.

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67. Yong-Tae Kwon KR, Wire arrayed chip size package.

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