이 특허를 인용한 특허 (86)

1. Wang, Chung Yu; Lee, Chien-Hsiun, Aluminum cap for reducing scratch and wire-bond bridging of bond pads.

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2. Charneski Lawrence J. ; Nguyen Tue, Copper adhered to a diffusion barrier surface.

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3. Anthony K. Stamper, Copper conductive line with redundant liner and method of making.

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4. Leon Ashley ; Hormazdyar M. Dalal ; Du Binh Nguyen ; Hazara S. Rathore ; Richard G. Smith, Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same.

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5. Farrar Paul A., Copper metallurgy in integrated circuits.

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6. Farrar, Paul A., Copper metallurgy in integrated circuits.

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7. Klein Richard K. ; Erb Darrell ; Avanzino Steven ; Cheung Robin ; Luning Scott ; Tracy Bryan ; Gupta Subhash ; Lin Ming-Ren, Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device.

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8. Farrar,Paul A., Electronic apparatus having a core conductive structure within an insulating layer.

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9. Agarwal, Vishnu Kumar, Encapsulated conductive pillar.

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10. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper and other metals.

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11. Farrar Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.

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12. Farrar, Paul A., Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals.

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13. Farrar,Paul A., Hplasma treatment.

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14. Tanaka, Yoichiro, Implementation of diffusion barrier in 3D memory.

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15. Farrar, Paul A., Integrated circuit and seed layers.

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16. Farrar,Paul A., Integrated circuit and seed layers.

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17. Farrar,Paul A., Integrated circuit and seed layers.

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18. Farrar Paul A., Integrated circuit with oxidation-resistant polymeric layer.

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19. Sukharev, Valeriy; Catabay, Wilbur G.; Lu, Hongqiang, Interconnect integration.

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20. Yang, Chih-Chao; Wang, Ping-Chuan; Wang, Yun-Yu, Interconnect structure having enhanced electromigration reliability and a method of fabricating same.

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21. Yin, Zhiping; Jost, Mark E., Interconnect structures with interlayer dielectric.

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22. Edward Crandal Cooney, III ; Cyprian Emeka Uzoh, Low resistivity tantalum.

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23. Maekawa Kazuyoshi,JPX, Manufacturing method of semiconductor device having high pressure reflow process.

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24. Farrar, Paul A., Mask on a polymer having an opening width less than that of the opening in the polymer.

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25. Chan, Elvis M.; Withers, Bradley S., Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition.

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26. Nogami Takeshi, Method and system for providing an interconnect having reduced failure rates due to voids.

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27. Yoshida,Hiroshi; Mikawa,Takumi, Method for fabricating nonvolatile semiconductor memory device.

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28. Tanaka, Yoichiro, Method for implementing diffusion barrier in 3D memory.

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29. Kim Young-sun (Seoul KRX) Park Young-wook (Suwon KRX), Method for interconnecting layers in semiconductor device.

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30. Ahn,Kie Y.; Forbes,Leonard, Method for making integrated circuits.

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31. Dubin, Valery, Method for making interconnects and diffusion barriers in integrated circuits.

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32. Tseng Horng-Huei,TWX, Method for manufacturing diffusion barrier layer.

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33. Liu Chung-Shi,TWX ; Yu Chen-Hua,TWX ; Bao Tien-I,TWX ; Jang Syun-Ming,TWX, Method for selective growth of Cu.sub.3 Ge or Cu.sub.5 Si for passivation of damascene copper structures and device manufactured thereby.

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34. Kishimoto Koji,JPX, Method of fabricating a semiconductor device.

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35. Kim Do Heyoung,KRX, Method of fabricating metal line structure.

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36. Huang Yuan-Chang,TWX ; Chang Kuan-Hui,TWX, Method of fabricating seamless tungsten plug employing tungsten redeposition and etch back.

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37. Agarwal, Vishnu Kumar, Method of forming an encapsulated conductive pillar.

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38. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.

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39. Ashley Leon ; Dalal Hormazdyar M. ; Nguyen Du Binh ; Rathore Hazara S. ; Smith Richard G., Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity.

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40. Kazuyuki Higashi JP; Noriaki Matsunaga JP; Hiroshi Toyoda JP; Akihiro Kajita JP; Tetsuo Matsuda JP; Hisashi Kaneko JP, Method of forming diffusion barrier for copper interconnects.

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41. Chan Lap ; Zheng Jia Zhen,SGX, Method of making a copper interconnect with top barrier layer.

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42. Spencer, Gregory S.; Crabtree, Philip E.; Denning, Dean J.; Junker, Kurt H.; Martin, Gerald A., Method of making a die with recessed aluminum die pads.

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43. Spencer, Gregory S.; Crabtree, Phillip E.; Denning, Dean J.; Junker, Kurt H.; Martin, Gerald A., Method of making a die with recessed aluminum die pads.

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44. Toyoda, Hiroshi; Matsuda, Tetsuo; Kaneko, Hisashi; Hirabayashi, Hideaki, Method of making multi-level wiring in a semiconductor device.

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45. Harada Akihiko,JPX ; Saito Takayuki,JPX, Method of manufacturing a semiconductor device.

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46. Chan Lap ; Zheng Jia Zhen,SGX, Method of manufacturing copper interconnect with top barrier layer.

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47. Toyoda, Hiroshi; Yano, Hiroyuki; Minamihaba, Gaku; Fukushima, Dai; Matsuda, Tetsuo; Kaneko, Hisashi, Method of manufacturing semiconductor device including two-step polishing operation for cap metal.

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48. Gupta Subhash,SGX ; Ho Paul Kwok Keung,SGX ; Zhou Mei Sheng,SGX ; Chockalingam Ramasamy,SGX, Method to avoid copper contamination during copper etching and CMP.

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49. Gupta Subhash,SGX ; Ho Kwok Keung Paul,SGX ; Zhou Mei-Sheng,SGX ; Chool Simon,SGX, Method to avoid copper contamination on the sidewall of a via or a dual damascene structure.

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50. Chan, Lap; Li, Sam Fong Yau; Ng, Hou Tee, Method to encapsulate copper plug for interconnect metallization.

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51. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.

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52. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.

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53. Ahn,Kie Y.; Forbes,Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.

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54. Boyanov, Boyan; Singh, Kanwal Jit, Methods and apparatuses to form self-aligned caps.

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55. Boyanov, Boyan; Singh, Kanwal Jit, Methods and apparatuses to form self-aligned caps.

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56. Ahn Kie Y. ; Forbes Leonard, Methods for making copper and other metal interconnections in integrated circuits.

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57. Ahn,Kie Y.; Forbes,Leonard, Methods for making copper and other metal interconnections in integrated circuits.

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58. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.

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59. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.

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60. Ahn,Kie Y.; Forbes,Leonard, Methods for making integrated-circuit wiring from copper, silver, gold, and other metals.

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61. Valery Dubin, Methods for making interconnects and diffusion barriers in integrated circuits.

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62. Ahn,Kie Y.; Forbes,Leonard; Eldridge,Jerome M., Multilevel copper interconnect with double passivation.

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63. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.

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64. Ahn,Kie Y.; Forbes,Leonard, Multilevel copper interconnects with low-k dielectrics and air gaps.

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65. Yakura James P., Non-linear circuit elements on integrated circuits.

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66. Yakura James P., Non-linear circuit elements on integrated circuits.

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67. Chan Lap ; Yap Kuan Pei,MYX ; Tee Kheng Chok,MYX ; Ip Flora S.,SGX ; Loh Wye Boon,MYX, Passivation of copper interconnect surfaces with a passivating metal layer.

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68. Lap Chan ; Kuan Pei Yap MY; Kheng Chok Tee MY; Flora S. Ip SG; Wye Boon Loh MY, Passivation of copper interconnect surfaces with a passivating metal layer.

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69. Ahn,Kie Y.; Forbes,Leonard, Selective electroless-plated copper metallization.

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70. Kevin C. Brown, Self-aligned copper interconnect architecture with enhanced copper diffusion barrier.

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71. Liao Kuan-Yang,TWX, Self-aligned metal nitride for copper passivation.

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72. Ohtsuka, Nobuyuki; Shimizu, Noriyoshi; Sakai, Hisaya; Nakao, Yoshiyuki; Kondo, Hiroki; Suzuki, Takashi, Semiconductor device.

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73. Ohtsuka,Nobuyuki; Shimizu,Noriyoshi; Sakai,Hisaya; Nakao,Yoshiyuki; Kondo,Hiroki; Suzuki,Takashi, Semiconductor device and method of manufacturing the same.

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74. Toyoda, Hiroshi; Yano, Hiroyuki; Minamihaba, Gaku; Fukushima, Dai; Matsuda, Tetsuo; Kaneko, Hisashi, Semiconductor device having a damascene type wiring layer.

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75. Farrar, Paul A., Structures and methods to enhance copper metallization.

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76. Farrar, Paul A., Structures and methods to enhance copper metallization.

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77. Farrar, Paul A., Structures and methods to enhance copper metallization.

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78. Farrar,Paul A., Structures and methods to enhance copper metallization.

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79. Farrar,Paul A., Structures and methods to enhance copper metallization.

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80. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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81. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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82. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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83. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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84. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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85. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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86. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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