[특허]Non-dissipative battery charger equalizer

Non-dissipative battery charger equalizer 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01M-010/46
출원번호	US-0080898 (1993-06-21)
발명자 / 주소	Brainard Gerald L. (San Jose CA)
출원인 / 주소	AST Research, Inc. (Irvine CA 02)
인용정보	피인용 횟수 : 53 인용 특허 : 0

초록 ▼

A battery charger is disclosed for recharging reusable batteries in a manner that prevents overcharging of the same. The charger includes a voltage source and non-dissipative shunt arrangement that can be customized to charge any number of batteries. The charger may be a current limiting power supply that is controlled by the voltage or charge state of the batteries being recharged. The non-dissipative shunt includes a pair of transistors for each pair of batteries and an inductor placed one end between the battery pair and another end between the transistor pair. An oscillator, having two phases of equal, but opposite phase, is used to control each transistor to apply charge to a given battery during one phase and then to allow the charge to equalize between the battery pair during the second phase. The equalization is continued until both batteries reach a full charge without overcharging any one battery.

대표청구항 ▼

A battery charger for recharging batteries comprising: a voltage source for generating a charging current having a limited voltage range; means for connecting N batteries in series with the voltage source; N-1 inductors for equalizing the charge from said voltage source amongst said N batteries, each inductor being connected between a respective battery pair and responsive to voltage levels of said batteries in said respective battery pair; N-1 transistor pairs, each transistor pair connecting in parallel to said respective battery pair and to a respective one of said inductors such that some current from the voltage source is alternately diverted amongst the batteries in said battery pair, thus enabling said inductor to equalize the charge between the batteries so paired; and an oscillator, generating a first phase and a second phase, nearly equal and opposite to said first phase, the first phase being connected to a first transistor in each of said transistor pairs and the second phase being connected to a second transistor in each transistor pair, both phases being substantially equal, but not overlapping in time, so that the transistors within each transistor pair are switched on and off alternately for substantially equal durations.

이 특허를 인용한 특허 (53)

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