이 특허를 인용한 특허 (87) 인용/피인용 타임라인 분석

1. Manning, Troy A.; Ball, Michael B., Apparatus and methods for coupling conductive leads of semiconductor assemblies.

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2. Troy A. Manning ; Michael B. Ball, Apparatus and methods for coupling conductive leads of semiconductor assemblies.

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3. Manning Troy A. ; Ball Michael B., Apparatus for electrically coupling bond pads of a microelectronic device.

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4. Tongbi Jiang ; Li Li, Apparatus for electroless plating a contact pad.

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5. Narita, Shoriki; Ikeya, Masahiko; Tsuboi, Yasutaka; Mae, Takaharu; Kanayama, Shinji, Bump formation method and bump forming apparatus for semiconductor wafer.

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6. Narita,Shoriki; Ikeya,Masahiko; Tsuboi,Yasutaka; Mae,Takaharu; Kanayama,Shinji, Bump formation method and bump forming apparatus for semiconductor wafer.

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7. Fjelstad, Joseph, Compliant package with conductive elastomeric posts.

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8. Kim, Chul-Hong, Composition, an electrode transfer film including the same, a display panel, and a method of forming an electrode.

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9. Shia, Rebecca; Chen, Jack Tsung-Yu, Conductive lithographic polymer and method of making devices using same.

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10. Cram, Daniel P., Conductive polymer contact system and test method for semiconductor components.

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11. Daniel P. Cram, Conductive polymer contact system and test method for semiconductor components.

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12. Akram, Salman, Copper interconnect.

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13. Akram,Salman, Copper interconnect.

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14. Akram,Salman, Copper interconnect.

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15. Akram,Salman, Copper interconnect for semiconductor device.

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16. Jiang,Tongbi; Li,Li, Device having contact pad with a conductive layer and a conductive passivation layer.

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17. Sakuyama, Seiki; Imaizumi, Nobuhiro; Yagi, Tomohisa, Electrode-to-electrode bond structure.

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18. Nguyen Guy P. ; Edwards Carl, Flexible interpenetrating networks formed by epoxy-cyanate ester compositions via a polyamide.

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19. Moran, John D.; Kruse, Blanca; Gamez Sanchez, Amilcar B., Flip chip structure and method of manufacture.

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20. Chen, Chih-Shun; Yuan, Po-Hao; Chiu, Shih-Kuang; Chien, Feng-Lung; Yang, Ke-Chuan, Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer.

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21. Kurita, Yoichiro; Ouchi, Rieka; Miyazaki, Takashi; Yamada, Toshiyuki, Flip-chip type semiconductor device.

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22. Kurita, Yoichiro; Ouchi, Rieka; Miyazaki, Takashi; Yamada, Toshiyuki, Flip-chip type semiconductor device.

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23. Farnworth Warren M., Hermetically sealed chip scale packages formed by wafer level fabrication and assembly.

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24. Kawashima, Kazuyuki; Tanaka, Yasunori, High-strength solder joint.

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25. Kawashima, Kazuyuki; Tanaka, Yasunori, High-strength solder joint.

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26. Koyama, Shuji; Kitani, Masashi; Mori, Toshihiro; Ozaki, Teruo; Kubota, Masahiko, Ink jet recording head, method for producing the same and recording apparatus equipped with the same.

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27. Zhao, Lily; Liang, Dexin, Integrated circuit package, ball-grid array integrated circuit package.

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28. Tzanavaras, George; Michael, Mihalis, Interconnect structure.

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29. Nguyen,My N., Interface materials and methods of production and use thereof.

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30. Roldan Judith Marie ; Saraf Ravi F., Lead-free interconnection for electronic devices.

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31. Inoue Yasushi,JPX ; Sugimoto Masakazu,JPX ; Mochizuki Amane,JPX, Low thermal expansion circuit board and multilayer wiring circuit board.

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32. Yasushi Inoue JP; Masakazu Sugimoto JP; Amane Mochizuki JP, Low thermal expansion circuit board and multilayer wiring circuit board.

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33. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.

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34. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.

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35. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.

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36. Jiang Tongbi ; Li Li, Method and apparatus for electroless plating a contact pad.

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37. Tongbi Jiang ; Li Li, Method and apparatus for electroless plating a contact pad.

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38. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.

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39. Jiang, Tongbi; Li, Li, Method for electroless plating a contact pad.

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40. Jiang, Tongbi; Li, Li, Method for electroless plating a contact pad.

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41. Farnworth Warren M., Method for fabricating electronic assemblies using semi-cured conductive elastomeric bumps.

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42. Tzanavaras George ; Michael Mihalis, Method for forming interconnects.

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43. Mitchell, Craig; Warner, Mike; Behlen, Jim, Method for making a semiconductor chip package.

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44. Yamashita, Yudai, Method for manufacturing conductive pattern substrate.

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45. Fey Edmond Otto ; Lyjak Kenneth Stanley ; Trevitt Donna Jean, Method of controlling the spread of an adhesive on a circuitized organic substrate.

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46. Yoda, Tsuyoshi, Method of fabricating bumps utilizing a resist layer having photosensitive agent and resin.

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47. David R. Hembree, Method of forming a solder ball.

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48. Hembree David R., Method of forming a solder ball.

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49. Kinoshita Makoto,JPX, Method of forming bump electrodes.

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50. Heo Young Wook,KRX, Method of forming chip bumps of bump chip scale semiconductor package.

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51. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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52. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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53. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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54. Ball Michael B., Method of improving interconnect of semiconductor device by utilizing a flattened ball bond.

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55. Ball Michael B., Method of improving interconnect of semiconductor devices by using a flattened ball bond.

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56. Michael B. Ball, Method of improving interconnect of semiconductor devices by using a flattened ball bond.

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57. Ball Michael B., Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond.

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58. Ball, Michael B., Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond.

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59. Sakuyama, Seiki; Imaizumi, Nobuhiro; Yagi, Tomohisa, Method of making electrode-to-electrode bond structure and electrode-to-electrode bond structure made thereby.

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60. Theuss, Horst, Method of manufacturing an integrated circuit.

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61. Farnworth,Warren M.; Brooks,Jerry M., Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation.

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62. Clevenger,Lawrence A.; Hsu,Louis L.; Radens,Carl J.; Wang,Li Kong; Wong,Kwong Hon, Method to fabricate passive components using conductive polymer.

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63. Rinne Glenn A. ; Lizzul Christine, Methods of electroplating solder bumps of uniform height on integrated circuit substrates.

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64. Fjelstad,Joseph, Methods of making microelectronic packages with conductive elastomeric posts.

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65. Zhao Lily ; Liang Dexin, Methods of packaging an integrated circuit and methods of forming an integrated circuit package.

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66. Zhao, Lily; Liang, Dexin, Methods of packaging an integrated circuit and methods of forming an integrated circuit package.

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67. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.

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68. Farnworth, Warren M., Methods of wafer level fabrication and assembly of chip scale packages.

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69. Booyens, Harry; Figov, Murray; Blondal, Daniel J.; West, Paul R., Micro-lens enhanced element.

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70. Albert, Jonathan D.; Gates, Holly G., Microencapsulated electrophoretic display with integrated driver.

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71. Albert,Jonathan D.; Gates,Holly G., Microencapsulated electrophoretic display with integrated driver.

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72. Caillat Patrice,FRX, Process for producing a sealing and mechanical strength ring between a substrate and a chip hybridized by bumps on the substrate.

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73. Hikita, Junichi; Shibata, Kazutaka; Ueda, Shigeyuki, Production process for semiconductor device.

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74. Hikita,Junichi; Shibata,Kazutaka; Ueda,Shigeyuki, Production process for semiconductor device.

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75. Ahmad Syed Sajid, Reduced filler particle size encapsulant for reduction in die surface damage in LOC packages and method of use.

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76. Ryo Enomoto JP; Hideo Yabashi JP; Tadashi Sugiyama JP; Kenzo Hatada JP, Semiconductor chip and method manufacturing the same.

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77. Akram, Salman, Semiconductor device having copper interconnect for bonding.

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78. Cram,Daniel P., Test method for semiconductor components using anisotropic conductive polymer contact system.

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79. Cram,Daniel P., Test method for semiconductor components using conductive polymer contact system.

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80. Fang,Ming; Dubin,Valery M.; Haight,Scott M., Tin deposition.

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81. Jiang, Tongbi, Underfill process.

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82. Farnworth, Warren M.; Akram, Salman, Use of palladium in IC manufacturing with conductive polymer bump.

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83. Farnworth,Warren M.; Akram,Salman, Use of palladium in IC manufacturing with conductive polymer bump.

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84. Gilleo Kenneth Burton ; Blumel David ; McLenaghan James, Wafer coating method for flip chips.

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85. Farnworth Warren M., Wafer level fabrication and assembly of chip scale packages.

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86. Standing, Martin, Wafer level underfill and interconnect process.

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87. Standing, Martin, Wafer level underfill and interconnect process.

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