$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method of making overpass mask/insulator for local interconnects 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/48
출원번호 US-0245997 (1994-05-19)
발명자 / 주소
  • Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT) Mann Randy W. (Jericho VT) Meulemans Darrell (Jericho VT) Starkey Gordon S. (Essex Junction VT)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 30  인용 특허 : 0

초록

Fabrication methods and resultant semiconductor structures wherein stack structures are selectively insulated from an enveloping layer of local interconnect material. The fabrication methods involve forming an overpass insulator(s) simultaneously with the underlying gate. Specifically, a layer of no

대표청구항

A method for fabricating a semiconductor structure, said method comprising the steps of: (a) damascening a first mask of electrically insulative material into an electrically conductive material; (b) forming a second mask above said electrically conductive material; (c) using both said first mask an

이 특허를 인용한 특허 (30)

  1. Akatsu Hiroyuki ; Divakaruni Ramachandra ; Lee Gill Yong, Disposable spacers for improved array gapfill in high density DRAMs.
  2. Rodgers T. J. ; Geha Sam ; Petti Chris ; Yen Ting-Pwu, Edge metal for interconnect layers.
  3. Lochtefeld, Anthony J.; Langdo, Thomas A.; Westhoff, Richard, Elevated source and drain elements for strained-channel heterojuntion field-effect transistors.
  4. Geha, Sam G., Hot metallization process.
  5. Harvey Ian, Integrated circuit device interconnection techniques.
  6. Harvey Ian Robert ; Lin Xi-Wei, Metallization technique for gate electrodes and local interconnects.
  7. Mizushima Kazuyuki,JPX, Method for manufacturing a through hole.
  8. Yen Ting, Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit.
  9. Armacost Michael D. ; Gambino Jeffrey Peter, Method of making a disposable corner etch stop-spacer for borderless contacts.
  10. Blosse, Alain; Thedki, Sanjay; Qiao, Jianmin; Gilboa, Yitzhak, Method of making metallization and contact structures in an integrated circuit.
  11. Alain Blosse ; Sanjay Thedki ; Jianmin Qiao ; Yitzhak Gilboa, Method of making metallization and contact structures in an integrated circuit comprising an etch stop layer.
  12. Fitzgerald, Eugene A., Methods of fabricating contact regions for FET incorporating SiGe.
  13. Langdo, Thomas A.; Lochtefeld, Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  14. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  15. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
  16. Currie,Matthew T.; Hammond,Richard, Methods of forming reacted conductive gate electrodes.
  17. Furukawa Toshiharu ; Hakey Mark C. ; Holmes Steven J. ; Horak David V. ; Nakos James S. ; Rabidoux Paul A., Process for fabricating short channel field effect transistor with a highly conductive gate.
  18. Currie, Matthew T.; Hammond, Richard, Reacted conductive gate electrodes.
  19. Currie,Matthew T.; Hammond,Richard, Reacted conductive gate electrodes.
  20. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  21. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  22. Xi-Wei Lin, Self-aligned etch-stop layer formation for semiconductor devices.
  23. Lin Xi-Wei, Self-aligned processing of semiconductor device features.
  24. Lin Xi-Wei ; Weling Milind Ganesh, Self-aligned silicidation technique to independently form silicides of different thickness on a semiconductor device.
  25. Tsunashima,Yoshitaka; Miyano,Kiyotaka; Ushiku,Yukihiro, Semiconductor device and method of manufacturing the same.
  26. Atsuki Ono JP, Semiconductor device having field effect transistors different in thickness of gate electrodes and process of fabrication thereof.
  27. Currie,Matthew T.; Lochtefeld,Anthony J., Shallow trench isolation process.
  28. Liang,Chunlin; Doyle,Brian S., Thermal conducting trench in a semiconductor structure.
  29. Liang,Chunlin; Doyle,Brian S., Thermal conducting trench in a semiconductor structure and method for forming the same.
  30. Hall, Mark D.; Abeln, Glenn C.; Grant, John M., Trench formation in a semiconductor material.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로