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Video processing module using a second programmable logic device which reconfigures a first programmable logic device fo 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0128494 (1993-09-28)
발명자 / 주소
  • Taylor Brad (Oakland CA)
출원인 / 주소
  • Giga Operations Corporation (Berkeley CA 02)
인용정보 피인용 횟수 : 344  인용 특허 : 0

초록 ▼

A video processing module designed for high performance using economical components. A programmable logic device (PLD) is configured to modify a data stream, in particular a video stream. The PLD can be connected to a memory resource. In addition, the PLD can be connected to a second PLD through an

대표청구항 ▼

A video processing system comprising: a video input bus, for carrying a stream of video data to the system, a video output bus, for carrying a stream of modified video data from the system, a video processing device comprising a first programmable logic device having an input connecting said first p

이 특허를 인용한 특허 (344)

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  166. Martin Vorbach DE; Robert Munch DE, Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--.
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  167. Vorbach, Martin; Nückel, Armin, Method for interleaving a program over a plurality of cells.
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  168. Vorbach, Martin; Nückel, Armin; May, Frank; Weinhardt, Markus; Cardoso, Joao Manuel Paiva, Method for processing data.
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  169. Vorbach Martin,DEX ; Munch Robert,DEX, Method for the automatic address generation of modules within clusters comprised of a plurality of these modules.
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  170. Vorbach, Martin; May, Frank; Nückel, Armin, Method for the translation of programs for reconfigurable architectures.
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  171. May,Frank; N？ckel,Armin; Vorbach,Martin, Method for translating programs for reconfigurable architectures.
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  172. Vorbach, Martin; Munch, Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.).
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  173. Vorbach,Martin; M체nch,Robert, Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.).
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  174. Vorbach, Martin; Munch, Robert, Method of repairing integrated circuits.
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  175. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable module.
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  176. Vorbach, Martin; Munch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  177. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  178. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  179. Vorbach, Martin; Münch, Robert M., Method of self-synchronization of configurable elements of a programmable module.
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  180. Vorbach,Martin; M체nch,Robert, Method of self-synchronization of configurable elements of a programmable module.
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  181. Vorbach, Martin; M?nch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  182. Vorbach, Martin; Munch, Robert, Method of self-synchronization of configurable elements of a programmable unit.
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  183. Vorbach Martin,DEX ; Munch Robert,DEX, Method of the self-synchronization of configurable elements of a programmable unit.
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  184. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  185. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
    상세보기
  186. Vorbach, Martin; Baumgarte, Volker, Methods and devices for treating and processing data.
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  187. Vorbach,Martin; Baumgarte,Volker, Methods and devices for treating and processing data.
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  188. Vorbach, Martin, Methods and devices for treating and/or processing data.
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  189. Silverbrook, Kia; Lapstun, Paul; Walmsley, Simon Robert, Modular camera and printer.
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  190. Ahern, Frank W.; Rhoden, Desi; Doss, Jeff; Mollo, Charles, Modular computer system.
    상세보기
  191. Ahern, Frank W.; Rhoden, Desi; Doss, Jeff; Mollo, Charles, Modular computer system.
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  192. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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  193. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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  194. Streicher, Keone; Langhammer, Martin; Lin, Yi-Wen; Leung, Wai-Bor; Lewis, David; Mauer, Volker; Lui, Henry Y.; Demirsoy, Suleyman Sirri; Yi, Hyun, Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry.
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  195. Arad, Eli, Motherboard with video data processing card capability.
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  196. Kassas, Zaher; Lewis, James M., Multi-channel algorithm infrastructure for programmable hardware elements.
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  197. Silverbrook, Kia, Multi-core image processor for portable device.
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  198. Silverbrook, Kia, Multi-core image processor for portable device.
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  199. Silverbrook, Kia, Multi-core processor for hand-held, image capture device.
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  200. Silverbrook, Kia, Multi-core processor for portable device with dual image sensors.
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  201. Silverbrook, Kia, Multi-core processor for portable device with dual image sensors.
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  202. Langhammer, Martin, Multi-operand floating point operations in a programmable integrated circuit device.
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  203. Langhammer, Martin, Multiple-precision processing block in a programmable integrated circuit device.
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  204. Choe, Kok Heng; Ngai, Tony K; Lui, Henry Y., Multiplier-accumulator circuitry and methods.
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  205. Wise, Adrian P; Sotheran, Martin W; Robbins, William P; Jones, Anthony M; Finch, Helen R; Boyd, Kevin J; Claydon, Anthony Peter J, Multistandard video decoder and decompression method for processing encoded bit streams according to respective different standards.
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  206. Wise, Adrian P.; Sotheran, Martin W.; Robbins, William P.; Jones, Anthony M.; Claydon, Anthony Peter John; Boyd, Kevin; Finch, Helen R., Multistandard video decoder and decompression system for processing encoded bit streams including a decoder with token generator and methods relating thereto.
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  207. Wise,Adrian P; Sotheran,Martin W; Robbins,William P; Jones,Anthony M; Finch,Helen R; Boyd,Kevin J; Claydon,Anthony Peter J, Multistandard video decoder and decompression system for processing encoded bit streams including a reconfigurable processing stage and methods relating thereto.
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  208. Wise, Adrian P.; Boyd, Kevin; Claydon, Anothy Peter; Robbins, William P.; Finch, Helen R.; Sotheran, Martin W.; Jones, Anthony Mark, Multistandard video decoder and decompression system for processing encoded bit streams including a standard-independent stage and methods relating thereto.
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  209. Wise,Adrian P; Sotheran,Martin W; Robbins,William P; Jones,Anthony M; Finch,Helen R; Boyd,Kevin J.; Clayton,Anthony Peter J, Multistandard video decoder and decompression system for processing encoded bit streams including a video formatter and methods relating thereto.
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  210. Wise, Adrian P; Sotheran, Martin W; Robbins, William P; Jones, Anthony M; Finch, Helen R; Boyd, Kevin J; Claydon, Anthony Peter J, Multistandard video decoder and decompression system for processing encoded bit streams including pipeline processing and methods relating thereto.
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  211. Wise, Adrian P; Sotheran, Martin W; Robbins, William P; Jones, Anthony M; Finch, Helen R; Boyd, Kevin J; Claydon, Anthony Peter J, Multistandard video decoder and decompression system for processing encoded bit streams including start code detection and methods relating thereto.
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  212. Sotheran,Martin W; Robbins,William P; Jones,Anthony M; Finch,Helen R; Boyd,Kevin J; Claydon,Anthony Peter J; Wise,Adrian P, Multistandard video decoder and decompression system for processing encoded bit streams including start codes and methods relating thereto.
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  213. Wise Adrian P,GBX ; Sotheran Martin W,GBX ; Robbins William P,GBX ; Jones Anthony M,NLX ; Finch Helen R,GBX ; Boyd Kevin J,GBX ; Claydon Anthony Peter J,GBX, Multistandard video decoder and decompression system for processing encoded bit streams including start codes and methods relating thereto.
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  214. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
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  215. Langhammer, Martin, Normalization of floating point operations in a programmable integrated circuit device.
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  216. Vorbach, Martin, Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization.
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  217. Wise Adrian P.,GBX ; Sotheran Martin W,GBX ; Robbins William P.,GBX, Picture start token.
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  218. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  219. Vorbach, Martin; Baumgarte, Volker; Ehlers, Gerd; May, Frank; Nückel, Armin, Pipeline configuration protocol and configuration unit communication.
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  220. Vorbach,Martin; Baumgarte,Volker; Ehlers,Gerd; May,Frank; N체ckel,Armin, Pipeline configuration unit protocols and communication.
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  221. Wise Adrian Philip,GBX, Pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus.
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  222. Wise Adrian P.,GBX ; Sotheran Martin W.,GBX ; Robbins William P.,GBX, Pipeline processing machine with interactive stages operable in response to tokens and system and methods relating thereto.
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  223. Mauer, Volker; Langhammer, Martin, Pipelined systolic finite impulse response filter.
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  224. Langhammer, Martin, Polynomial calculations optimized for programmable integrated circuit device structures.
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  225. Silverbrook, Kia, Portable device with dual image sensors and quad-core processor.
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  226. Silverbrook, Kia, Portable device with dual image sensors and quad-core processor.
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  227. Silverbrook, Kia, Portable device with image sensor and quad-core processor for multi-point focus image capture.
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  228. Silverbrook, Kia, Portable device with image sensor and quad-core processor for multi-point focus image capture.
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  229. Silverbrook, Kia, Portable device with image sensors and multi-core processor.
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  230. Silverbrook, Kia, Portable device with image sensors and multi-core processor.
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  231. Silverbrook, Kia, Portable device with image sensors and multi-core processor.
    상세보기
  232. Silverbrook, Kia; Lapstun, Paul, Portable hand-held device for deblurring sensed images.
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  233. Silverbrook, Kia, Portable hand-held device for displaying oriented images.
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  234. Silverbrook, Kia, Portable hand-held device for displaying oriented images.
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  235. Silverbrook, Kia, Portable hand-held device for displaying oriented images.
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  236. Silverbrook, Kia; Lapstun, Paul, Portable hand-held device for manipulating images.
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  237. Silverbrook, Kia, Portable hand-held device having networked quad core processor.
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  238. Silverbrook, Kia, Portable hand-held device having quad core image processor.
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  239. Silverbrook, Kia, Portable hand-held device having quad core image processor.
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  240. Silverbrook, Kia, Portable hand-held device having quad core image processor.
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  241. Silverbrook, Kia, Portable hand-held device having stereoscopic image camera.
    상세보기
  242. Silverbrook, Kia, Portable hand-held device having stereoscopic image camera.
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  243. Silverbrook, Kia, Portable hand-held device having stereoscopic image camera.
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  244. Silverbrook, Kia, Portable handheld device with multi-core image processor.
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  245. Silverbrook, Kia, Portable handheld device with multi-core image processor.
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  246. Silverbrook, Kia, Portable handheld device with multi-core image processor.
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  247. Silverbrook, Kia, Portable handheld device with multi-core image processor.
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  248. Silverbrook, Kia, Portable handheld device with multi-core image processor.
    상세보기
  249. Silverbrook, Kia, Portable handheld device with multi-core image processor.
    상세보기
  250. Silverbrook, Kia, Portable handheld device with multi-core microcoded image processor.
    상세보기
  251. Silverbrook, Kia, Portable handheld device with multi-core microcoded image processor.
    상세보기
  252. Silverbrook, Kia, Portable imaging device with multi-core processor.
    상세보기
  253. Silverbrook, Kia, Portable imaging device with multi-core processor.
    상세보기
  254. Silverbrook, Kia, Portable imaging device with multi-core processor and orientation sensor.
    상세보기
  255. King, Tobin Allen; Silverbrook, Kia, Print media cartridge with ink supply manifold.
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  256. Vorbach Martin,DEX ; Munch Robert,DEX, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like).
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  257. Vorbach, Martin; Münch, Robert, Process for automatic dynamic reloading of data flow processors (DFPs) and units with two- or three-dimensional programmable cell architectures (FPGAs, DPGAs, and the like).
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  258. Martin Vorbach DE; Robert Munch DE, Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like).
    상세보기
  259. Vorbach, Martin, Processor arrangement on a chip including data processing, memory, and interface elements.
    상세보기
  260. Vorbach, Martin; Münch, Robert, Processor chip for reconfigurable data processing, for processing numeric and logic operations and including function and interconnection control units.
    상세보기
  261. Vorbach, Martin; Nückel, Armin, Processor chip including a plurality of cache elements connected to a plurality of processor cores.
    상세보기
  262. Bennett Toby D. ; Bishop James W. ; Davis Donald J. ; Harris Jonathan C., Programmable circuit assembly and methods for high bandwidth data processing.
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  263. Langhammer, Martin, Programmable device using fixed and configurable logic to implement floating-point rounding.
    상세보기
  264. Langhammer, Martin, Programmable device using fixed and configurable logic to implement recursive trees.
    상세보기
  265. Mauer, Volker; Langhammer, Martin, Programmable device with specialized multiplier blocks.
    상세보기
  266. Langhammer, Martin, QR decomposition in an integrated circuit device.
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  267. Mauer, Volker, QR decomposition in an integrated circuit device.
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  268. Silverbrook, Kia, Quad-core camera processor.
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  269. Silverbrook, Kia, Quad-core image processor.
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  270. Silverbrook, Kia, Quad-core image processor.
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  271. Silverbrook, Kia, Quad-core image processor.
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  272. Silverbrook, Kia, Quad-core image processor for device with image display.
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  273. Silverbrook, Kia, Quad-core image processor for facial detection.
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  274. Ledzius, Robert C.; Flemmons, James L.; Maturo, Lawrence R., Reconfigurable computing system and method and apparatus employing same.
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  275. Natoli, Vincent D.; Richie, David A., Reconfigurable computing system that shares processing between a host processor and one or more reconfigurable hardware modules.
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  276. Vorbach, Martin, Reconfigurable elements.
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  277. Vorbach, Martin, Reconfigurable elements.
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  278. Vorbach, Martin; Baumgarte, Volker, Reconfigurable general purpose processor having time restricted configurations.
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  279. Odom,Brian Keith; Peck,Joseph E.; Andrade,Hugo A.; Butler,Cary Paul; Truchard,James J.; Petersen,Newton G.; Novacek,Matthew, Reconfigurable measurement system utilizing a programmable hardware element and fixed hardware resources.
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  280. Vorbach,Martin; M？nch,Robert, Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells.
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  281. Vorbach, Martin, Reconfigurable sequencer structure.
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  282. Vorbach, Martin, Reconfigurable sequencer structure.
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  283. Vorbach, Martin, Reconfigurable sequencer structure.
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  284. Vorbach, Martin, Reconfigurable sequencer structure.
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  285. Vorbach,Martin, Reconfigurable sequencer structure.
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  286. Andrade,Hugo A.; Odom,Brian Keith; Ryan,Arthur, Reconfigurable test system.
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  287. Ryan Arthur ; Andrade Hugo, Reconfigurable test system.
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  288. Vorbach, Martin; Bretz, Daniel, Router.
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  289. Vorbach,Martin; Bretz,Daniel, Router.
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  290. Vorbach Martin,DEX ; Munch Robert,DEX, Run-time reconfiguration method for programmable units.
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  291. Vorbach,Martin; M？nch,Robert, Run-time reconfiguration method for programmable units.
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  292. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
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  293. Vorbach, Martin; Münch, Robert, Runtime configurable arithmetic and logic cell.
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  294. Ahern Frank, Serially linked bus bridge for expanding access over a first bus to a second bus.
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  295. Schultz, Kevin L.; Steger, Perry; Breyer, Stefanie, Smart camera with a plurality of slots for modular expansion capability through a variety of function modules connected to the smart camera.
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  296. Schultz,Kevin L.; Steger,Perry; Breyer,Stefanie, Smart camera with a plurality of slots for modular expansion capability through a variety of function modules connected to the smart camera.
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  297. Schultz, Kevin L.; Steger, Perry; Breyer, Stefanie, Smart camera with modular expansion capability including a function module that performs image processing.
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  298. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
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  299. Metzgen, Paul, Software-to-hardware compiler with symbol set inference analysis.
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  300. Langhammer, Martin; Dhanoa, Kulwinder, Solving linear matrices in an integrated circuit device.
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  301. Langhammer, Martin, Specialized processing block for implementing floating-point multiplier with subnormal operation support.
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  302. Xu, Lei; Mauer, Volker; Perry, Steven, Specialized processing block for programmable integrated circuit device.
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  303. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Lin, Yi-Wen, Specialized processing block for programmable logic device.
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  304. Langhammer, Martin; Lee, Kwan Yee Martin; Azgomi, Orang; Streicher, Keone; Pelt, Robert L., Specialized processing block for programmable logic device.
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  305. Langhammer, Martin; Lee, Kwan Yee Martin; Nguyen, Triet M.; Streicher, Keone; Azgomi, Orang, Specialized processing block for programmable logic device.
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  306. Lee, Kwan Yee Martin; Langhammer, Martin; Lin, Yi-Wen; Nguyen, Triet M., Specialized processing block for programmable logic device.
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  307. Lee, Kwan Yee Martin; Langhammer, Martin; Nguyen, Triet M.; Lin, Yi-Wen, Specialized processing block for programmable logic device.
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  308. Langhammer, Martin, Specialized processing block with fixed- and floating-point structures.
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  309. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for execution by multiple targets.
    상세보기
  310. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., Specifying and targeting portions of a graphical program for real-time response.
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  311. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., Specifying portions of a graphical program for respective execution by a processor and a programmable hardware element.
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  312. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian K.; Butler, Cary P., System and method for configuring a device to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
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  313. Chandhoke, Sundeep; Vazquez, Nicolas; Schultz, Kevin L., System and method for configuring a hardware device to execute a prototype.
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  314. Peck,Joseph E.; Novacek,Matthew; Andrade,Hugo A.; Petersen,Newton G., System and method for configuring a reconfigurable system.
    상세보기
  315. Kodosky Jeffrey L. ; Andrade Hugo ; Odom Brian K. ; Butler Cary P., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
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  316. Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul; Schultz, Kevin L., System and method for configuring an instrument to perform measurement functions utilizing conversion of graphical programs into hardware implementations.
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  317. Zeidman, Robert M., System and method for connecting a logic circuit simulation to a network.
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  318. Kodosky,Jeffrey L.; Andrade,Hugo; Odom,Brian K.; Butler,Cary P., System and method for converting a graphical program including a structure node into a hardware implementation.
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  319. Radl, Brad, System and method for creating a graphical control programming environment.
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  320. Schultz, Kevin L.; Kodosky, Jeffrey L.; Andrade, Hugo; Odom, Brian Keith; Butler, Cary Paul, System and method for deploying a graphical program on an image acquisition device.
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  321. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware.
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  322. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.
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  323. Eslick,Ian S.; Williams,Mark; French,Robert S., System and method for executing hybridized code on a dynamically configurable hardware environment.
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  324. Johnson, III, Rousey; Fuchs, Stephen; Tschepen, Tracey, System and method for rotating images.
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  325. Ahern,Frank W., System enabling device communication in an expanded computing device.
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  326. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX ; Robbins William P.,GBX, System for microprogrammable state machine in video parser clearing and resetting processing stages responsive to flush token generating by token generator responsive to received data.
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  327. Wise Adrian P.,GBX ; Sotheran Martin William,GBX ; Robbins William P.,GBX, System for microprogrammable state machine in video parser disabling portion of processing stages responsive to sequence.
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  328. Sullam, Bert S.; Snyder, Warren S.; Mohammed, Haneef D., System level interconnect with programmable switching.
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  329. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
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  330. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
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  331. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.
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  332. Wise Adrian Philip,GBX ; Sotheran Martin William,GBX ; Robbins William P.,GBX, Technique for initiating processing of a data stream of encoded video information.
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  333. Ilic, Kosta; Blasig, Dustyn K., Testing a graphical program intended for a programmable hardware element.
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  334. Wise Adrian P.,GBX ; Dewar Kevin D.,GBX ; Jones Anthony Mark,GBX ; Sotheran Martin William,GBX ; Smith Colin,GBX ; Finch Helen Rosemary,GBX ; Claydon Anthony Peter John,GBX ; Patterson Donald William, Token-based adaptive video processing arrangement.
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  335. Martin Vorbach DE; Robert Munch DE, UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAY.
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  336. Snyder, Warren; Sullam, Bert; Mohammed, Haneef, Universal digital block interconnection and channel routing.
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  337. Zeidman, Robert Marc, Use of hardware peripheral devices with software simulations.
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  338. Kasuya Atsushi, Verification system for circuit simulator.
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  339. Spektor, Evgeny; Elias, Gili, Video data processing circuits and systems comprising programmable blocks or components.
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  340. Guermoud, Hassane; Jolly, Emmanuel; Blondé, Laurent; Kervec, Jonathan, Video data processing module furnished with a configurable video processing unit with a single input bus.
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  341. Wise Adrian P.,GBX ; Birch Nicholas,GBX, Video decompression.
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  342. Wise Adrian Philip,GBX, Video decompression and decoding system utilizing control and data tokens.
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  343. Park Kyun-Hoe,KRX, Video overlay image converter.
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  344. Wise Adrian P.,GBX ; Boyd Kevin J.,GBX ; Finch Helen R,GBX ; Robbins William P,GBX, Video parser.
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