이 특허를 인용한 특허 (45)

1. Wiese, Michael L., Adaptive throughput optimization.

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2. Larson, Chad J.; Mata, Jr., Ricardo; Perez, Michael A.; Vongvibool, Steven, Adjusting direction of data flow between I/O bridges and I/O hubs based on real time traffic levels.

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3. Seconi Mark (Phoenix AZ) Mc Allister Paul (Chandler AZ) Hall Andrew (Hillsboro OR) Jalfon Marc (Haifa ILX), Apparatus and method for performing arbitration and data transfer over multiple buses.

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4. Devereux Ian Victor,GBX, Asynchronous first-in-first-out buffer circuit burst mode control.

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5. Marshall, John William, Attribute based memory pre-fetching technique.

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6. Cho Han-Jin,KRX ; Choi Young-Gyoo,KRX, Communication system for selecting a communication transmission method.

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7. Brey,Thomas M.; Frazier,Giles R.; Pfister,Gregory F.; Recio,Renato J.; Still,Gregory S., Determining server resources accessible to client nodes using information received at the server via a communications medium.

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8. David,Howard S., Distributed memory module cache writeback.

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9. Potter, Kenneth H., Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system.

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10. Rooney Jeffrey Jay, Dynamic buffer allocation for a computer system.

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11. Rooney, Jeffrey Jay, Dynamic buffer allocation for a computer system.

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12. Marshall, John William; Potter, Kenneth H., Group and virtual locking mechanism for inter processor synchronization.

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13. Jain, Satchit; Cho, Sung-Soo, Initializing a memory controller by executing software in second memory to wakeup a system.

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14. Collins Michael J. ; Thome Gary W. ; Moriarty Michael P. ; Ramsey Jens K. ; Larson John E., Memory controller including write posting queues, bus read control logic, and a data contents counter.

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15. Gai, Silvano; Edsall, Thomas J., Method and apparatus for high-speed parsing of network messages.

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16. Gai,Silvano; Edsall,Thomas J., Method and apparatus for high-speed parsing of network messages.

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17. Hass, David T., Method and apparatus for implementing cache coherency of a processor.

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18. Priem Curtis, Method and apparatus for providing high quality audio in a computer system.

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19. Burton, Robert; Wang, Jennifer; Joshi, Aniruddha, Method and system for monitoring DMA status.

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20. Joseph Jeddeloh, Method for memory error handling.

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21. Jain, Satchit; Cho, Sung-Soo, Method of initializing a memory controller by executing software in a second memory to wake up a system.

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22. Mukai Akira,JPX ; Masui Norio,JPX, Method of processing interrupt requests and information processing apparatus using the method.

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23. Dey Shankar ; Bui Dinh Kim ; Zhao Ming, Microprocessor system having multiplexor disposed in first and second read paths between memory CPU and DMA for selecti.

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24. Temma Shoji,JPX ; Funaki Jun,JPX, Processor apparatus and its control method for controlling a processor having a CPU for executing an instruction accord.

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25. Davis Eric R. ; Brown David R., Qualified burst cache for transfer of data between disparate clock domains.

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26. Gary Thomas Bastian ; Kevin Michael Rishavy ; Martin Gerard Gravenstein ; Robert Lee Anderson ; Rollie Morris Fisher ; Raymond Allen Stevens ; Samuel James Guido, Queued port data controller for microprocessor-based engine control applications.

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27. Kawasumi Atsushi,JPX ; Miyano Shinji,JPX, Semiconductor memory device with multiplied internal clock.

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28. Liu,Chuan; Hsiao,Chuan Cheng; Tsai,Jeng Horng, Signal generating circuit capable of generating a validation signal and related method thereof.

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29. Marcotte Scott Thomas, System and method for application influence of I/O service order post I/O request.

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30. Rooney, Jeffrey Jay, System and method for dynamic buffer allocation.

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31. Heil Thomas F. ; Francis Martin H. ; DeKoning Rodney A. ; Weber Bret S., System and method for peer-to-peer accelerated I/O shipping between host bus adapters in clustered computer network.

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32. Odom Brian Keith (Travis County TX) Canik Robert (Cedar Park TX), System and method for performing efficient random write operations.

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33. Liu Young Way ; Huang Chin-I ; Lee Ta-Yung,TWX ; Chou Wen-Ching Andy ; Wang Dean C. ; Liu Ming-Kang, System and method for reducing latency in software modem for high-speed synchronous transmission.

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34. Jeddeloh Joseph, System for accelerating memory bandwidth.

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35. Brown Lawrence Marcel (San Jose CA) Finney Damon W. (San Jose CA) Marenin George Bohoslaw (San Jose CA) Yanes Adalberto Guillermo (Sunnyvale CA), System for controlling responses to requests over a data bus between a plurality of master controllers and a slave stora.

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36. Rooney Jeffrey Jay, System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair.

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37. Kou James Tai-Ling, System for handling an asynchronous interrupt a universal serial bus device.

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38. Jeddeloh Joseph, System for memory error handling.

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39. Jeddeloh Joseph, System for method memory error handling.

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40. Poisner David I., System for programming peripheral with address and direction information and sending the information through data bus or.

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41. Hansen John P. ; Typaldos Melanie D. ; Stott Louis R., System for selecting between internal and external DMA request where ASP generates internal request is determined by at.

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42. Whitney Mark M., System for, and method of, off-loading network transactions from a mainframe to an intelligent input/output device, including off-loading message queuing facilities.

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43. Collins Michael J. (Tomball TX) Thome Gary W. (Tomball TX) Moriarty Michael P. (Spring TX) Ramsey Jens K. (Houston TX) Larson John E. (Katy TX), System having a plurality of posting queues associated with different types of write operations for selectively checking.

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44. Kantor, Jiri; Patterson, Andrew; Bevis, Paul; Turvey, David; McMillan, Craig; Sadler, Andrew, Systems and methods for multi-stage message brokering.

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45. Kantor, Jiri; Patterson, Andrew; Bevis, Paul; Turvey, David; McMillan, Craig; Sadler, Andrew, Systems and methods for transaction messaging brokering.

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