이 특허를 인용한 특허 (48)

1. Chen,Hsien Wei, Bond pad structure for integrated circuit chip.

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2. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.

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3. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.

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4. Lee,Jin Yuan; Lin,Mou Shiung; Huang,Ching Cheng, Chip structure and process for forming the same.

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5. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.

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6. Lin,Mou Shiung; Lee,Jin Yuan; Huang,Ching Cheng, Chip structure and process for forming the same.

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7. Icher,Fran？ois; Dehos,Bruno, Circuitry for protecting electronic circuits against electrostatic discharges and methods of operating the same.

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8. Ola Pettersson SE, Electronic discharge protection of integrated circuits.

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9. Male, Barry Jon; Cook, Benjamin; Neidorff, Robert Alan; Kummerl, Steve, Electronic sensors with sensor die in package structure cavity.

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10. Yang,Nian; Ogawa,Hiroyuki; Wu,Yider; Chang,Kuo Tung; Sun,Yu, Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto .

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11. Cook, Benjamin Stassen; Male, Barry Jon; Neidorff, Robert Alan, Galvanic isolation device.

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12. Venkitachalam, Girish; Rahim, Irfan; McElheny, Peter John, Integrated circuit bond pad structures.

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13. Righter,Alan W, Integrated circuit bond pad structures and methods of making.

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14. Righter,Alan W., Integrated circuit bond pad structures and methods of making.

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15. Downey, Harold A.; Downey, Susan H.; Miller, James W., Integrated circuit die I/O cells.

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16. Vo, Nhat D.; Tran, Tu-Anh N.; Carpenter, Burton J.; Hong, Dae Y.; Miller, James W.; Phillips, Kendall D., Integrated circuit having pads and input/output (I/O) cells.

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17. Pozder,Scott K.; Hess,Kevin J.; Leung,Pak K.; Travis,Edward O.; Wilkerson,Brett P.; Wontor,David G.; Zhao,Jie Hua, Integrated circuit having structural support for a flip-chip interconnect pad and method therefor.

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18. Voldman, Steven H., Interconnect structure encased with high and low k interlevel dielectrics.

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19. Voldman,Steven H., Interconnect structure encased with high and low k interlevel dielectrics.

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20. Male, Barry Jon; Cook, Benjamin; Neidorff, Robert Alan; Kummerl, Steve, Isolator integrated circuits with package structure cavity and fabrication methods.

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21. Hess, Kevin J.; Downey, Susan H.; Miller, James W.; Yong, Cheng Choi, Method and apparatus for providing structural support for interconnect pad while allowing signal conductance.

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22. Hess,Kevin J.; Downey,Susan H.; Miller,James W.; Yong,Cheng Choi, Method and apparatus for providing structural support for interconnect pad while allowing signal conductance.

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23. Hively James W., Method of fabricating a microelectronic package having polymer ESD protection.

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24. Gay, Laurent; Guyader, Francois; Diette, Frederic, Microelectronic chip, component containing such a chip and manufacturing method.

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25. Hively James W., Microelectronic device with thin film electrostatic discharge protection structure.

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26. Hively James W., Microelectronic package with polymer ESD protection.

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27. Hunter, Stevan G.; Rasmussen, Bryce A.; Ruud, Troy L., Pad over interconnect pad structure design.

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28. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Post passivation interconnection schemes on top of the IC chips.

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29. Vogel, Martin J.; Nelson, Richard J.; Firth, Robert A.; Falco, Anthony D.; Schulman, Joseph H., Protection apparatus for implantable medical device.

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30. Vogel,Martin J.; Nelson,Richard J.; Firth,Robert A.; Falco,Anthony D.; Schulman,Joseph H.; Chu,Lung Hsi; Mandell,Lee J., Protection apparatus for implantable medical device.

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31. Downey, Susan H.; Harper, Peter R.; Hess, Kevin; Leoni, Michael V.; Tran, Tu-Anh, Semiconductor device having a bond pad and method therefor.

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32. Yong, Lois E.; Harper, Peter R.; Tran, Tu Anh; Metz, Jeffrey W.; Leal, George R.; Dinh, Dieu Van, Semiconductor device having a bond pad and method therefor.

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33. Yong,Lois E.; Harper,Peter R.; Tran,Tu Anh; Metz,Jeffrey W.; Leal,George R.; Van Dinh,Dieu, Semiconductor device having a bond pad and method therefor.

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34. Takemura, Koji; Hirano, Hiroshige; Takahashi, Masao; Sano, Hikari; Itoh, Yutaka; Koike, Koji, Semiconductor device having a pad and plurality of interconnects.

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35. Downey, Susan H.; Miller, James W.; Hall, Geoffrey B., Semiconductor device having a wire bond pad and method therefor.

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36. Downey, Susan H.; Miller, James W.; Hall, Geoffrey B., Semiconductor device having a wire bond pad and method therefor.

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37. Takemura, Koji; Hirano, Hiroshige; Takahashi, Masao; Sano, Hikari; Itoh, Yutaka; Koike, Koji, Semiconductor device having pads and which minimizes defects due to bonding and probing processes.

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38. Yang, Hyang-Ja, Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection.

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39. Suzuki, Shinya; Higuchi, Kazuhisa, Semiconductor device with signal wirings and dummy wirings that pass through under electrode pads and in which the number of dummy wirings near the peripheral portion of the device being greater than at a more centrally located portion.

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40. Suzuki, Shinya; Higuchi, Kazuhisa, Semiconductor device with signal wirings that pass through under the output electrode pads and dummy wirings near the peripheral portion.

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41. Noto Takayuki,JPX ; Oi Eiji,JPX ; Shiotsuki Yahiro,JPX ; Kato Kazuo,JPX ; Ohagi Hideki,JPX, Semiconductor integrated circuit device.

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42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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45. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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46. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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47. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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48. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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