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Semiconductor memory device having thin film transistor and method of producing the same 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-011/412
출원번호 US-0373502 (1995-01-17)
발명자 / 주소
  • Ema Taiji (Kawasaki JPX) Itabashi Kazuo (Kawasaki JPX)
출원인 / 주소
  • Fujitsu Limited (Kawasaki JPX 03)
인용정보 피인용 횟수 : 56  인용 특허 : 0

초록

A thin film transistor (TFT) load type static random access memory (SRAM) which includes a memory capacitor in addition to the stray capacitance. The SRAM includes a semiconductor substrate and a memory cell provided on the semiconductor substrate. The memory cell includes first and second transfer

대표청구항

A semiconductor memory device comprising a semiconductor substrate and a memory cell provided on the semiconductor substrate, the memory cell comprising: first and second transfer transistors, each having a source region, a drain region and a gate electrode; first and second driver transistors, each

이 특허를 인용한 특허 (56)

  1. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
  2. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
  3. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
  4. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
  5. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  6. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  7. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  8. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  9. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  10. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
  13. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
  14. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  15. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
  16. Datta, Suman; Doyle, Brian S.; Chau, Robert S.; Kavalieros, Jack; Zheng, Bo; Hareland, Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
  17. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
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  19. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  20. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  21. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
  22. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
  23. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
  24. Nishida,Akio; Yoshida,Yasuko; Ikeda,Shuji, Method of manufacturing a semiconductor integrated circuit device.
  25. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
  26. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
  27. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Datta,Suman; Jin,Been Yih, Nonplanar device with stress incorporation layer and method of fabrication.
  28. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
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  55. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
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