[특허]Process for fabricating a complementary MIS transistor

Process for fabricating a complementary MIS transistor 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/265
출원번호	US-0280922 (1994-07-26)
우선권정보	JP-0125606 (1992-04-17)
발명자 / 주소	Katada Mitsutaka (Kariya JPX) Muramoto Hidetoshi (Nagoya JPX) Fuzino Seizi (Toyota JPX) Hattori Tadashi (Okazaki JPX) Abe Katsunori (Obu JPX)
출원인 / 주소	Nippondenso Co., Ltd. (Kariya JPX 03)
인용정보	피인용 횟수 : 79 인용 특허 : 0

초록 ▼

A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.

대표청구항 ▼

A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion regions have an impurity concentration level that is higher than an impurity concentration level in said P-type well and said N-type well, and such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well from a first edge and a second edge of said insulating gate, said step of forming said N-type diffusion regions being conducted, in each of said P-type well and said N-type well, by applying an ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well, and such that said N-type source region and said N-type drain region have a depth at least equal to a depth of said N-type diffusion region in said P-type well, said step of forming said N-type source region and said N-type drain region being conducted in self-alignment to said insulating gate provided on said P-type well, such that said N-type source region and said N-type drain region have respective junctions defining a lateral boundary thereof, respectively in alignment to said first and second edges of said insulating gate on said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said N-type well, and such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well, said step of forming said P-type source region and said P-type drain region being conducted in self-alignment to said insulating gate provided on said N-type well, such that said P-type source region and said P-type drain region have respective junctions defining a lateral boundary thereof, respectively in alignment to said first and second edges of said insulating gate on said N-type well.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Process for fabricating a complementary MIS transistor 원문보기

초록 ▼

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Process for fabricating a complementary MIS transistor 원문보기

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이 특허를 인용한 특허 (79)

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