[특허]Method and apparatus for fault tolerant fast writes through buffer dumping

Method and apparatus for fault tolerant fast writes through buffer dumping 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-011/00
출원번호	US-0363655 (1994-12-22)
발명자 / 주소	Brant William A. (Boulder CO) Neben Gary (Boulder CO) Nielson Michael E. (Broomfield CO) Stallmo David C. (Boulder CO)
출원인 / 주소	EMC Corporation (Hopkinton MA 02)
인용정보	피인용 횟수 : 76 인용 특허 : 0

초록 ▼

An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i.e., Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails. A backup power source is provided to ensure that power will be available to at least one of the two memories such that the data that has been received within the controller will always be accessible. Accordingly, since the data will be accessible, even if of a failure of any single component or power source occurs, the controller may acknowledge the write operation requested by the CPU as soon as data is successfully written to both the DATA-RAM and the SHADOW-RAM.

대표청구항 ▼

An array controller system for controlling a Write operation for an array of data storage units, including: (a) an array controller processor for controlling the Writing of pending Write data to the array of data storage units; (b) a first communications adapter, coupled to the array controller processor, for receiving pending Write data from a host over a first communications bus and writing the pending Write data to the array of data storage units over the first communications bus under the control of the array controller processor; (c) a first memory device for storing pending Write data; (d) a first memory interface, coupled to the first memory device, the array controller processor, the communications adapter, and a second communications bus, for: (1) receiving pending Write data from the first communications adapter and storing in the first memory device the received pending Write data; (2) reading, under control of the array controller processor, pending Write data from the first memory device and coupling the read pending Write data to the first communications adapter for completing the Write to the array of data storage units; (3) controlling communications with an external device, the communications being sent over the second communications bus, such that pending Write data stored within the first memory device can be read and communicated to the external device via the second communications bus upon a failure of the array controller processor.

이 특허를 인용한 특허 (76)

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연합인증

Method and apparatus for fault tolerant fast writes through buffer dumping 원문보기

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Method and apparatus for fault tolerant fast writes through buffer dumping 원문보기

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