초록 ▼

A phase comparator, a loop filter and a VCO compose a PLL. In the phase comparator, a CMI code defined by a CMI data is synchronized with a VCO clock generated in the VCO and an inverted clock of the VCO clock, respectively, to provide first and second synchronized CMI codes. The first synchronized

A phase comparator, a loop filter and a VCO compose a PLL. In the phase comparator, a CMI code defined by a CMI data is synchronized with a VCO clock generated in the VCO and an inverted clock of the VCO clock, respectively, to provide first and second synchronized CMI codes. The first synchronized CMI code is delayed to provide a delayed CMI code by a predetermined time dependent on a period of the VCO clock. The first and second synchronized CMI codes are subject to an exclusive OR logic calculation, thereby generating a phase difference signal. The delayed CMI code and the first synchronized CMI code are subject to an exclusive OR logic calculation, and a result of this exclusive OR logic calculation and the VCO clock are subject to an AND logic calculation to provide an enable signal. Only when the enable signal is high, the phase difference signal is sampled to be used as a phase difference signal in the PLL.

대표청구항 ▼

A phase comparator, comprising: a first flip flop for synchronizing a coded mark inversion (CMI) code with a voltage controlled oscillator (VCO) clock, said CMI code being defined by a CMI data and said VCO clock having a period for defining a time slot for said CMI data; a second flip flop for dela

A phase comparator, comprising: a first flip flop for synchronizing a coded mark inversion (CMI) code with a voltage controlled oscillator (VCO) clock, said CMI code being defined by a CMI data and said VCO clock having a period for defining a time slot for said CMI data; a second flip flop for delaying said CMI code supplied from said first flip flop by a predetermined time determined by said period of said VCO clock; a first exclusive OR circuit for performing exclusive OR logic calculation between outputs of said first and second flip flops; a third flip flop for adjusting a timing of said CMI code by a signal obtained by inverting said VCO clock; a second exclusive OR circuit for performing exclusive OR logic calculation between outputs of said first and third flip flops, said second exclusive OR circuit providing a pulse signal representing a phase difference between said CMI code and said VCO clock; an AND gate for performing AND logic calculation between an output of said first exclusive OR circuit and said VCO clock, said AND gate providing an enable signal having first and second logic states; and an output circuit for outputting said pulse signal supplied from said second exclusive OR circuit by receiving said first logic state of said enable signal, said output circuit having one output line on which a three state signal of said pulse signal is provided.