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Memory partitioning 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-013/00
출원번호 US-0421321 (1995-04-13)
발명자 / 주소
  • Lau Winnie K. W. (Shapin HKX) Malinowski Richard (Placerville CA)
출원인 / 주소
  • LSI Logic Corporation (Milpitas CA 02)
인용정보 피인용 횟수 : 37  인용 특허 : 0

초록

This invention relates to an improved memory storage system which allows selective ranges of memory locations, which can also be referred to as virtual memory banks, to be enabled and disabled. The ranges of memory locations can be disabled to avoid refreshing unused memory location and to eliminate

대표청구항

In a computer system having an address bus and a data bus, a memory storage system comprising: main memory means comprising a plurality of memory locations for storing groups of data from the data bus and later retrieving the groups of data, each memory location having a unique address and being add

이 특허를 인용한 특허 (37)

  1. Jeddeloh, Joseph, Accelerated graphics port for a multiple memory controller computer system.
  2. Jeddeloh,Joseph, Accelerated graphics port for a multiple memory controller computer system.
  3. Jeddeloh Joseph, Accelerated graphics port for multiple memory controller computer system.
  4. A. Kent Porterfield, Apparatus comprising a translation lookaside buffer for graphics address remapping of virtual addresses.
  5. Porterfield, A. Kent, Apparatus for extending the available number of configuration registers.
  6. Michael Joseph Carnevale, Arranging address space to access multiple memory banks.
  7. Ashmore, Paul Andrew; Davies, Ian Robert; Maine, Gene; Vedder, Rex Weldon, Certified memory-to-memory data transfer between active-active raid controllers.
  8. Kelleher, Brian, Design, layout, and manufacturing techniques for multivariant integrated circuits.
  9. Porterfield A. Kent, GART and PTES defined by configuration registers.
  10. Porterfield A. Kent, GART and PTES defined by configuration registers.
  11. Skidmore,Beth E., Memory device and method having banks of different sizes.
  12. Skidmore,Beth E., Memory device and method having banks of different sizes.
  13. Skidmore,Beth E., Memory device and method having banks of different sizes.
  14. Skidmore,Beth E., Memory device and method having banks of different sizes.
  15. Davies, Ian Robert; Pecone, Victor Key, Method for adopting an orphan I/O port in a redundant storage controller.
  16. Porterfield A. Kent, Method for extending the available number of configuration registers.
  17. Porterfield A. Kent, Method for extending the available number of configuration registers.
  18. Jeddeloh Joseph, Method of implementing an accelerated graphics port for a multiple memory controller computer system.
  19. Jeddeloh, Joseph, Method of implementing an accelerated graphics port for a multiple memory controller computer system.
  20. Jeddeloh, Joseph, Method of implementing an accelerated graphics port for a multiple memory controller computer system.
  21. Jeddeloh, Joseph, Method of implementing an accelerated graphics port for a multiple memory controller computer system.
  22. Jeddeloh, Joseph, Method of implementing an accelerated graphics/port for a multiple memory controller computer system.
  23. Boles, Edward Brian; Drake, Rodney; Johansen, Darrel; Mitra, Sumit; Triece, Joseph; Yach, Randy, Microcontroller instruction set.
  24. Boles,Edward Brian; Drake,Rodney Jay; Johansen,Darrel Ray; Mitra,Sumit K.; Yach,Randy; Grosbach,James; Conner,Joshua M.; Triece,Joseph W., Microcontroller instruction set.
  25. Boles,Edward Brian; Drake,Rodney; Johansen,Darrel; Mitra,Sumit; Triece,Joseph; Yach,Randy, Microcontroller instruction set.
  26. Lau, Winnie; Perets, Ronen, Mirror addressing in a DSP.
  27. Kellogg Mark W. ; Dell Timothy J. ; Hedberg Erik L. ; Bertin Claude L., Reconfigurable I/O DRAM.
  28. Ashmore, Paul Andrew, Redundant storage controller system with enhanced failure analysis capability.
  29. Davies, Ian Robert, Safe message transfers on PCI-Express link from RAID controller to receiver-programmable window of partner RAID controller CPU memory.
  30. Tadaaki Yamauchi JP, Semiconductor integrated circuit capable of reducing area occupied by data bus.
  31. Kultursay, Emre; Ebcioglu, Kemal; Kandemir, Mahmut Taylan, Storage unsharing.
  32. Bennett, Alan; Gorobets, Sergey Anatolievich, System and method for bank logical data remapping.
  33. Davies, Ian Robert, System and method for sharing SATA drives in active-active RAID controller system.
  34. Porterfield A. Kent, System for accelerated graphics port address remapping interface to main memory.
  35. Porterfield A. Kent, System for extending the available number of configuration registers.
  36. Kelleher, Brian; Kilgariff, Emmett M.; Yamamoto, Wayne, Techniques for balancing accesses to memory having different memory types.
  37. Kelleher, Brian; Kilgariff, Emmett, Techniques for different memory depths on different partitions.
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