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Transfer processor with transparency 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-013/00
출원번호 US-0208413 (1994-03-08)
발명자 / 주소
  • Guttag Karl M. (Sugar Land TX) Read Christopher J. (Houston TX) Poland Sydney W. (Katy TX) Gove Robert J. (Plano TX) Golston Jeremiah E. (Sugar Land TX)
출원인 / 주소
  • Texas Instruments Incorporated (Dallas TX 02)
인용정보 피인용 횟수 : 55  인용 특허 : 0

초록

Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be transferred. A comparator compares recalled data to stored transparency data and indicates whether dat

대표청구항

A data processor comprising: a memory having plurality of storage locations; a transparency register storing transparency data, said transparency register storing an integral multiple of a minimum amount of data to be transferred, said transparency data being repeated within transparency register sa

이 특허를 인용한 특허 (55)

  1. Mahan, Justin Michael; Hutchins, Edward A.; Toksvig, Michael J. M., Address independent shader program loading.
  2. Aguilar, Jr., Maximino; Day, Michael Norman; Nutter, Mark Richard; Stafford, James Michael, Asymmetric heterogeneous multi-threaded operating system.
  3. Minor, Barry L; Nutter, Mark Richard; To, VanDung Dang, Balancing computational load across a plurality of processors.
  4. Minor,Barry L; Nutter,Mark Richard; To,VanDung Dang, Balancing computational load across a plurality of processors.
  5. Larson Michael Kerry ; McDonald Timothy James, Circuits systems and methods for managing data requests between memory subsystems operating in response to multiple address formats.
  6. Karandikar, Ashish; Agarwal, Pooja, Configurable SIMD engine with high, low and mixed precision modes.
  7. Karandikar, Ashish; Gadre, Shirish; Gruner, Frederick R.; Sijstermans, Franciscus W., Context switching on a video processor having a scalar execution unit and a vector execution unit.
  8. Brokenshire, Daniel Alan; Hofstee, Harm Peter; Minor, Barry L; Nutter, Mark Richard, Dynamically partitioning processing across a plurality of heterogeneous processors.
  9. Brokenshire,Daniel Alan; Hofstee,Harm Peter; Minor,Barry L; Nutter,Mark Richard, Dynamically partitioning processing across plurality of heterogeneous processors.
  10. Yabumoto Masahiro,JPX, Emulator with function for detecting illegal access to special function register.
  11. Da Silva, Manoel Henrique, Enhancements introduced in a portable moisture meter device for remote use.
  12. Dye Thomas Anthony (Austin TX), Graphics accelerator with dual memory controllers.
  13. Aguilar, Jr., Maximino; Day, Michael Norman; Nutter, Mark Richard; Xenidis, James, Grouping processors and assigning shared memory space to a group in a heterogeneous computer environment.
  14. Crow, Franklin C.; Sewall, Jeffrey R., Interrupt handling techniques in the rasterizer of a GPU.
  15. Crow, Franklin C.; Sewall, Jeffrey R., Interrupt handling techniques in the rasterizer of a GPU.
  16. Karandikar, Ashish; Gadre, Shirish; Lew, Stephen D., Latency tolerant system for executing video processing operations.
  17. Aguilar, Jr., Maximino; Chow, Alex Chunghen; Day, Michael Norman; Gowen, Michael Stan; Nutter, Mark Richard; Xenidis, James, Loading software on a plurality of processors.
  18. Aguilar, Jr.,Maximino; Chow,Alex Chunghen; Day,Michael Norman; Gowen,Michael Stan; Nutter,Mark Richard; Xenidis,James, Loading software on a plurality of processors.
  19. Bradley L. Taylor, Local memory unit system with global access for use on reconfigurable chips.
  20. Aguilar, Jr., Maximino; Day, Michael Norman; Nutter, Mark Richard; Stafford, James Michael, Managing a plurality of processors as devices.
  21. Wentka Mark J. ; Sher Richard A., Memory interface device.
  22. Danskin, John M.; Tamasi, Anthony Michael, Method and system for implementing fragment operation processing across a graphics bus interconnect.
  23. Bowen, Andrew D., Method and system for non stalling pipeline instruction fetching from memory.
  24. Karandikar, Ashish; Gadre, Shirish; Salek, Amir H., Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions.
  25. Lew, Stephen D.; Karandikar, Ashish; Gadre, Shirish; Sijstermans, Franciscus W., Multi context execution on a video processor.
  26. Karandikar, Ashish; Gadre, Shirish; Lew, Stephen D.; Cheng, Christopher T., Multidimensional datapath processing in a video processor.
  27. Garg, Atul; Sharma, Anil, Multistandard hardware video encoder.
  28. Kanuri, Mrudula, Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory.
  29. Karandikar, Ashish; Gadre, Shirish; Sijstermans, Franciscus W.; Su, Zhiqiang Jonathan, Pipelined L2 cache for memory transfers for a video processor.
  30. Vamanan, Balajee; Methar, Tukaram; Kanuri, Mrudula; Krishnan, Sreenivas, Processing of read requests in a memory controller using pre-fetch mechanism.
  31. Aguilar, Jr., Maximino; Nutter, Mark Richard; Stafford, James Michael, Processor dedicated code handling in a multi-processor environment.
  32. Aguilar, Jr., Maximino; Nutter, Mark Richard; Stafford, James Michael, Processor dedicated code handling in a multi-processor environment.
  33. Mahan, Justin Michael; Hutchins, Edward A.; Kubalska, Ewa M.; Battle, James T., Program sequencer for generating indeterminant length shader programs for a graphics processor.
  34. Lew, Stephen D.; Gadre, Shirish; Karandikar, Ashish; Sijstermans, Franciscus W., Programmable DMA engine for implementing memory transfers and video processing for a video processor.
  35. Venkatrao,Balakrishna, Reducing resource consumption by ineffective write operations.
  36. Venkatrao,Balakrishna, Reducing resource consumption by ineffective write operations in a shared memory system.
  37. Moriwaki, Shohei; Azekawa, Yoshifumi; Chiba, Osamu; Shimakawa, Kazuhiro, Rendering processing apparatus requiring less storage capacity for memory and method therefor.
  38. Garg, Atul; Venkatapuram, Prahlad, Rewind-enabled hardware encoder.
  39. Mahan, Justin Michael; Hutchins, Edward A., Shader program instruction fetch.
  40. Mahan, Justin Michael; Hutchins, Edward A., Software assisted shader merging.
  41. Su, Zhiqiang Jonathan; Karandikar, Ashish, State machine control for a pipelined L2 cache to implement memory transfers for a video processor.
  42. Gadre, Shirish; Karandikar, Ashish; Lew, Stephen D., Stream processing in a video processor.
  43. Park Heon-Chul,KRX, System and method for efficient packing data into an output buffer.
  44. Aguilar, Jr.,Maximino; Day,Michael Norman; Nutter,Mark Richard; Xenidis,James, System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment.
  45. Aguilar, Jr.,Maximino; Nutter,Mark Richard; Stafford,James Michael, System and method for processor thread acting as a system service processor.
  46. Aguilar, Jr.,Maximino; Manning,Sidney James; Nutter,Mark Richard; Stafford,James Michael, System and method for processor thread for software debugging.
  47. Gilbertson Roger Lee, System and method for programmably controlling data transfer request rates between data sources and destinations in a data processing system.
  48. Aguilar, Jr.,Maximino; Craft,David; Day,Michael Norman; Hatakeyama,Akiyuki; Hofstee,Harm Peter; Suzuoki,Masakazu, System and method for selecting and using a signal processor in a multiprocessor system to operate as a security for encryption/decryption of data.
  49. Nutter,Mark Richard; To,VanDung Dang, System and method for solving a large system of dense linear equations.
  50. Brokenshire,Daniel Alan; Day,Michael Norman; Minor,Barry L; Nutter,Mark Richard; To,VanDung Dang, Task queue management of virtual devices using a plurality of processors.
  51. Michael Joseph Azevedo ; Roger Gregory Hathorn ; Andrew Dale Walls, Transfer progress alert module.
  52. Luu, Viet-Tam; Pflughaupt, Russell, Validating a graphics pipeline using pre-determined schedules.
  53. Gadre, Shirish; Karandikar, Ashish; Lew, Stephen D.; Cheng, Christopher T., Video processor having scalar and vector components.
  54. Brokenshire,Daniel Alan; Day,Michael Norman; Minor,Barry L; Nutter,Mark Richard, Virtual devices using a pluarlity of processors.
  55. Brokenshire, Daniel Alan; Day, Michael Norman; Minor, Barry L; Nutter, Mark Richard, Virtual devices using a plurality of processors.
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