초록 ▼

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field effect transistor pair, each including a source and a drain region with a gate contact positioned therebetween, ohmic contacts to the sources, and a rectify

Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field effect transistor pair, each including a source and a drain region with a gate contact positioned therebetween, ohmic contacts to the sources, and a rectifying junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two rectifying contacts are interconnected as the output of the device. The structure includes a semiconductor substrate having slow diffusant dopants therein or implanted metal ions of cobalt, molybdenum, or tungsten. The structure further includes an epitaxial semiconductor layer with resistance on the order of 0.5 to 1.0 ohm cm and a thickness of 1.5 to 5.0 m

대표청구항 ▼

A merged emitter BICMOS integrated device structure comprising a semiconductor body including a doped epitaxial layer on a heavier doped substrate, said substrate having a first major surface on which said epitaxial layer is formed and a second major surface opposing said first major surface, a P-ch

A merged emitter BICMOS integrated device structure comprising a semiconductor body including a doped epitaxial layer on a heavier doped substrate, said substrate having a first major surface on which said epitaxial layer is formed and a second major surface opposing said first major surface, a P-channel field effect transistor in a first device region in said epitaxial layer and abutting a surface of said epitaxial layer, an N-channel field effect transistor in a second device region in said epitaxial layer and abutting said surface of said epitaxial layer, and a positive voltage contact on said second major surface for supplying current through said substrate to said P-channel field effect transistor whereby switch back effect in said P-channel field effect transistor is reduced.