초록 ▼

A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating tra

A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device. The bias circuit may control the slew rate of an output driver, may control the propagation delay through a delay element, and be used to control the duration of a pulse produced by a pulse generating circuit.

대표청구항 ▼

A circuit for producing a compensated bias voltage in an integrated circuit, comprising: a resistor divider coupled between a power supply voltage and a reference voltage, for producing a divided voltage; a current mirror, having a reference leg and an output leg, wherein the current through the ref

A circuit for producing a compensated bias voltage in an integrated circuit, comprising: a resistor divider coupled between a power supply voltage and a reference voltage, for producing a divided voltage; a current mirror, having a reference leg and an output leg, wherein the current through the reference leg is controlled by the divided voltage, and wherein the output leg comprises: a mirror transistor, for conducting a mirrored current corresponding to the current through the reference leg; and a load for conducting the mirrored current and for producing a bias voltage at a bias output node responsive to the mirrored current; and a pass gate, coupled between the voltage divider and the current mirror, for disconnecting the voltage divider from the current mirror responsive to a disable signal.