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[미국특허] Microelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/10
  • H01L-027/118
출원번호 US-0333367 (1994-11-02)
발명자 / 주소
  • Scepanovic Ranko (San Jose CA) Koford James S. (San Jose CA) Kudryavstev Valeriy B. (Moscow RUX) Andreev Alexander E. (Moskovskaja RUX) Aleshin Stanislav V. (Moscow RUX) Podkolzin Alexander S. (Mosco
출원인 / 주소
  • LIS Logic Corporation (Milpitas CA 02)
인용정보 피인용 횟수 : 147  인용 특허 : 6

초록 ▼

Electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit extend in three directions that are angularly displaced from each other by 60°. The conductors pass through points defined by centers of closely packed hexagons superimposed on the circuit such that

대표청구항 ▼

A microelectronic structure, comprising: a substrate; a plurality of microelectronic cells formed on the substrate, each cell including at least one serrated edge defined by edges of a plurality of closely packed hexagons superimposed on the substrate, each cell comprising an interconnection termina

이 특허에 인용된 특허 (6) 인용/피인용 타임라인 분석

  1. Chamberlain John T. (Macclesfield GB2), Constant-distance structure polycellular very large scale integrated circuit.
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  2. Lidow Alexander (Manhattan Beach CA) Herman Thomas (Redondo Beach CA) Rumennik Vladimir (El Segundo CA), Plural polygon source pattern for mosfet.
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  3. Neilson John M. S. (Norristown PA) Jones Frederick P. (Mountaintop PA) Yedinak Joseph A. (Wilkes-Barre PA) Rexer Christopher L. (Mountaintop PA), Power FET with gate segments covering drain regions disposed in a hexagonal pattern.
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  4. Klodzinski Stanley J. (White Haven PA) Ronan ; Jr. Harold R. (Mountaintop PA) Neilson John M. S. (Norristown PA) Wheatley ; Jr. Carl F. (Drums PA), Power MOSFET.
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  5. Shimoyama Hiroyoshi (Amagasaki JPX), Semiconductor integrated circuit.
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  6. Yuyama Kyoji (Shiroyama JPX) Kawaji Mikinori (Hino JPX), Semiconductor integrated circuit device with improved connection pattern of signal wirings.
    상세보기

이 특허를 인용한 특허 (147) 인용/피인용 타임라인 분석

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  4. Scepanovic Ranko ; Koford James S. ; Andreev Alexander E.,RUX, Advanced modular cell placement system with coarse overflow remover.
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  49. Teig,Steven; Ganley,Joseph L., Method and apparatus for considering diagonal wiring in placement.
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  50. Pavisic Ivan ; Scepanovic Ranko ; Andreev Alexander E.,RUX, Method and apparatus for continuous column density optimization.
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  51. Teig, Steven; Caldwell, Andrew, Method and apparatus for costing a path expansion.
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  52. Teig, Steven; Frankle, Jonathan, Method and apparatus for costing routes of nets.
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  54. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a region of an integrated circuit layout.
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  55. Teig,Steven; Caldwell,Andrew, Method and apparatus for decomposing a region of an integrated circuit layout.
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  56. Teig, Steven; Caldwell, Andrew, Method and apparatus for defining vias.
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  58. Teig, Steven; Caldwell, Andrew, Method and apparatus for determining viability of path expansions.
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  90. Teig, Steven; Buset, Oscar; Lin, Yang-Trung, Method and apparatus for producing sub-optimal routes for a net by generating fake configurations.
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  91. Teig, Steven; Caldwell, Andrew, Method and apparatus for propagating a function.
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  92. Teig, Steven; Caldwell, Andrew, Method and apparatus for propagating a piecewise linear function to a line.
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  93. Teig, Steven; Caldwell, Andrew, Method and apparatus for propagating a piecewise linear function to a point.
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  94. Teig,Steven; Caldwell,Andrew, Method and apparatus for propagating a piecewise linear function to a surface.
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  96. Teig, Steven; Caldwell, Andrew, Method and apparatus for proportionate costing of vias.
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  147. Rostoker Michael D. ; Koford James S. ; Scepanovic Ranko ; Jones Edwin R. ; Padmanahben Gobi R. ; Kapoor Ashok K. ; Kudryavtsev Valeriv B.,RUX ; Andreev Alexander E.,RUX ; Aleshin Stanislav V.,RUX ; , Tri-directional interconnect architecture for SRAM.
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