초록 ▼

A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency p

A high frequency power FET device (22) is integrated with passive components (23,24,26,28,31), an electro-static discharge (ESD) device (27,127,227), and/or a logic structure (29) on a semiconductor body (13) to form a monolithic high frequency integrated circuit structure (10). The high frequency power FET device (22) includes a grounded source configuration. The logic structure (29) utilizes the high frequency power FET structure in a grounded source configuration as one device in a CMOS implementation.

대표청구항 ▼

A monolithic high frequency integrated circuit structure comprising: a semiconductor body including a substrate of a first conductivity type and a first layer of the first conductivity type formed on the substrate, the substrate having a higher dopant concentration than the first layer, wherein the

A monolithic high frequency integrated circuit structure comprising: a semiconductor body including a substrate of a first conductivity type and a first layer of the first conductivity type formed on the substrate, the substrate having a higher dopant concentration than the first layer, wherein the first layer is isolated into a plurality of active areas by a plurality of passivation regions; a high frequency power FET device formed in a first active area, the high frequency power FET device including a first source region of a second conductivity type, a first drain region of the second conductivity type spaced apart from the first source region, a first gate electrode layer between the first source region and the first drain region and separated from the first layer by a first gate dielectric layer, and a first sinker region of the first conductivity type formed in the first layer and connecting the first source region to the substrate; and a series capacitor structure including a bottom plate formed on one of the plurality of passivation regions, a dielectric layer formed on the bottom plate, and a top plate formed on the dielectric layer.