이 특허를 인용한 특허 (64)

1. Enicks, Darwin Gene; Carver, Damian, Bandgap and recombination engineered emitter layers for SiGe HBT performance optimization.

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2. Enicks,Darwin Gene; Carver,Damian, Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement.

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3. Ellis-Monaghan, John Joseph; Joseph, Alvin Jose; Liu, Qizhi; Peterson, Kirk David, BiCMOS technology on SOI substrates.

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4. Franosch,Martin; Meister,Thomas; Schaefer,Herbert; Stengl,Reinhard, Bipolar transistor and method for fabricating it.

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5. Heinemann, Bernd; Ehwald, Karl-Ernst; Knoll, Dieter, Bipolar transistor and method for producing same.

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6. Kang, Jin Yeong; Lee, Seung Yun; Cho, Kyoung Ik, Bipolar transistor, BiCMOS device, and method for fabricating thereof.

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7. Bae, Geum-jong; Choe, Tae-hee; Kim, Sang-su; Rhee, Hwa-sung; Lee, Nae-in; Lee, Kyung-wook, CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same.

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8. Bae, Geum-jong; Choe, Tae-hee; Kim, Sang-su; Rhee, Hwa-sung; Lee, Nae-in; Lee, Kyung-wook, CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same.

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9. Bae, Geum-jong; Choe, Tae-hee; Kim, Sang-su; Rhee, Hwa-sung; Lee, Nae-in; Lee, Kyung-wook, CMOS integrated circuit devices and substrates having unstrained silicon active layers.

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10. Cai, Jin; Chang, Leland; Sleight, Jeffrey W., Complementary SOI lateral bipolar for SRAM in a CMOS platform.

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11. Cai, Jin; Chang, Leland; Sleight, Jeffrey W., Complementary SOI lateral bipolar for SRAM in a CMOS platform.

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12. Cai, Jin; Ning, Tak H., Complementary SOI lateral bipolar for SRAM in a low-voltage CMOS platform.

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13. Cai, Jin; Dennard, Robert H.; Haensch, Wilfried E.; Ning, Tak H., Complementary bipolar inverter.

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14. Cai, Jin; Dennard, Robert H.; Haensch, Wilfried E.; Ning, Tak H., Complementary bipolar inverter.

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15. Adkisson, James W.; Stamper, Anthony K., Contact module for optimizing emitter and contact resistance.

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16. Bryant,Andres; Lasky,Jerome B.; Leobandung,Effendi; Schepis,Dominic J., Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet.

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17. Freeman, Gregory G.; Greenberg, David R.; Jeng, Shwu-Jen, Dual sidewall spacer for a self-aligned extrinsic base in SiGe heterojunction bipolar transistors.

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18. Chen, Huajie; Chidambarrao, Dureseti; Schepis, Dominic J.; Utomo, Henry K., Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer.

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19. Chen,Huajie; Chidambarrao,Dureseti; Schepis,Dominic J.; Utomo,Henry K., Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer.

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20. Mori Hideki,JPX ; Gomi Takayuki,JPX, Heterojunction bipolar semiconductor device.

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21. Ozkan, Cengiz S.; Salmi, Abderrahmane, Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe).

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22. Swanson, Leland; Howard, Gregory E., High breakdown voltage transistor and method.

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23. Sheridan,David C.; Gray,Peter B.; Johnson,Jeffrey B.; Liu,Qizhi, High performance integrated vertical transistors and method of making the same.

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24. Jumpertz, Reiner; Schimpf, Klaus, Integrated SiGe NMOS and PMOS transistors.

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25. Tezuka, Tsutomu; Kawakubo, Takashi; Sugiyama, Naoharu, Integrated circuit device.

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26. Babcock, Jeffrey A.; Howard, Gregory E.; Pinto, Angelo; Steinmann, Phillipp; Balster, Scott G., Integrated process for high voltage and high performance silicon-on-insulator bipolar devices.

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27. Babcock, Jeffrey A.; Howard, Gregory E; Pinto, Angelo; Steinmann, Phillipp; Balster, Scott G., Integrated process for high voltage and high performance silicon-on-insulator bipolar devices.

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28. Babcock, Jeffrey A.; Pinto, Angelo; Howard, Gregory E., Lateral heterojunction bipolar transistor.

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29. Divakaruni, Ramachandra; Houghton, Russell J.; Mandelman, Jack A.; Pricer, Wilbur D.; Tonti, William R., Logic SOI structure, process and application for vertical bipolar transistor.

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30. Enicks,Darwin Gene, Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement.

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31. Douglas D. Coolbaugh ; James S. Dunn ; Peter J. Geiss ; Peter B. Gray ; David L. Harame ; Kathryn T. Schonenberg ; Stephen A. St. Onge ; Seshadri Subbanna, Method for epitaxial bipolar BiCMOS.

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32. Lee Jong Ho,KRX ; Lyu Jong Son,KRX ; Kim Bo Woo,KRX, Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy.

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33. Dietrich, Harry; Dudek, Volker; Schueppen, Andreas, Method for manufacturing a silicon wafer.

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34. Dietrich, Harry; Dudek, Volker; Schueppen, Andreas, Method for manufacturing buried areas.

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35. Dietrich, Harry; Dudek, Volker; Schueppen, Andreas, Method for manufacturing components of an SOI wafer.

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36. Howard, David; Racanelli, Marco; U'Ren, Greg D., Method for reducing extrinsic base resistance and improving manufacturability in an NPN transistor.

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37. Hsu, Sheng Teng; Tweet, Douglas James; Ulrich, Bruce Dale; Ying, Hong, Method of fabricating high performance SiGe heterojunction bipolar transistor BiCMOS on a silicon-on-insulator substrate.

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38. Bin Yu ; William G. En ; Judy Xilin An ; Concetta E. Riccobene, Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer.

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39. Krivokapic, Zoran; Buynoski, Matthew, Method of making a self-aligned triple gate silicon-on-insulator device.

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40. Ohta, Hiroyuki, Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate.

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41. Ohta, Hiroyuki, Method of manufacturing a semiconductor device including epitaxially growing semiconductor epitaxial layers on a surface of semiconductor substrate.

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42. Cho Deok Ho,KRX ; Lee Soo Min,KRX ; Han Tae Hyeon,KRX ; Ryum Byung Ryul,KRX ; Pyun Kwang Eui,KRX, Method of manufacturing a silicon/silicon germanium heterojunction bipolar transistor.

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43. Bae,Geum jong; Choe,Tae hee; Kim,Sang su; Rhee,Hwa sung; Lee,Nae in; Lee,Kyung wook, Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein.

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44. Howard,David; Racanelli,Marco; U'Ren,Greg D., NPN transistor having reduced extrinsic base resistance and improved manufacturability.

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45. Jones, Lyle, Oxide epitaxial isolation.

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46. Harame, David L.; Liu, Qizhi, PNP bipolar junction transistor fabrication using selective epitaxy.

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47. Harame, David L.; Liu, Qizhi, PNP bipolar junction transistor fabrication using selective epitaxy.

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48. Cai, Jin; Chan, Kevin K.; Ning, Tak H.; Yau, Jeng-Bang, SOI lateral bipolar transistors having surrounding extrinsic base portions.

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49. Leslie, Terrence C., Selective epitaxy in vertical integrated circuit.

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50. Leslie,Terrence C., Selective epitaxy vertical integrated circuit components.

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51. Leslie, Terrence C., Selective epitaxy vertical integrated circuit components and methods.

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52. Voldman, Steven H., Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement.

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53. Krivokapic, Zoran; Buynoski, Matthew, Self-aligned triple gate silicon-on-insulator (SOI) device.

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54. Sugiyama, Naoharu; Tezuka, Tsutomu; Mizuno, Tomohisa; Takagi, Shinichi, Semiconductor device.

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55. Sato, Fumihiko, Semiconductor device with reduced electrical variation.

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56. Aoki, Nobutoshi; Mizushima, Ichiro; Ohuchi, Kazuya, Semiconductor integrated circuit including insulated gate field effect transistor and method of manufacturing the same.

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57. Yu, Bin; van Bentum, Ralf, Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions.

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58. Bin Yu ; Ralf van Bentum DE, Semiconductor-on-insulator (SOI) device having source/drain silicon-germanium regions and method of manufacture.

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59. Yu, Bin; En, William G.; An, Judy Xilin; Riccobene, Concetta E., Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding.

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60. Chan,Kevin K.; Khater,Marwan H.; Schonenberg,Kathryn T.; Siddhartha,Panda, Structure and method for making heterojunction bipolar transistor having self-aligned silicon-germanium raised extrinsic base.

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61. Chen, Huajie; Chidambarrao, Dureseti; Dokumaci, Omer O.; Yang, Haining S., Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions.

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62. Zhu, En Jun, Structure for a semiconductor device.

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63. Kondo,Takayuki, Transistor and electronic device.

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64. Boles Timothy ; O'Keefe Matthew F. ; Sledziewski John M., Ultrahigh vacuum deposition of silicon (Si-Ge) on HMIC substrates.

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