[특허]Ball grid array integrated circuit package with thermal conductor

[미국특허] Ball grid array integrated circuit package with thermal conductor 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/10
출원번호	US-0245146 (1994-05-16)
발명자 / 주소	Marrs Robert C. (Scottsdale AZ) Molnar Ronald J. (Phoenix AZ)
출원인 / 주소	Amkor Electronics, Inc. (Chandler AZ 02)
인용정보	피인용 횟수 : 185 인용 특허 : 0

초록 ▼

A ball grid array package and low cost method for manufacture of the same is disclosed herein. The ball grid array package includes a thermal conductor which is a linearly co-extensive outer layer of an interconnection substrate and forms the outer surface of the ball grid array package. An integrated circuit chip is positioned on the underside of the package in a well region. The well region is either formed directly in the interconnection substrate or is formed by the application of a dam. The well region is then filled with an insulating encapsulant material to a predetermined level.

대표청구항 ▼

A packaged integrated circuit device, comprising: an interconnection substrate having one layer of conductive trace material and one layer of insulating material formed in or on said interconnection substrate, wherein said interconnection substrate has a first surface and a second surface opposite said first surface, said second surface of said interconnection substrate having a plurality of electrical contacts arranged in rows that are electrically connected to said one layer of conductive trace material for making electrical connections from said conductive trace material to contact points external to said packaged integrated circuit device; a metallic thermal conductor, said thermal conductor having a first surface attached to said first surface of said interconnection substrate, said thermal conductor having a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, wherein a thickness of said thermal conductor between said first surface and said second surface of said thermal conductor is less than 1.0 millimeter, and said thermal conductor is linearly co-extensive with said interconnection substrate first surface; a well region formed in said interconnection substrate, said well region having a bottom which is an exposed portion of said first surface of said thermal conductor; an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached in said well region such that said second surface of said integrated circuit chip and said portion of said first surface of said thermal conductor exposed at said bottom of said well region are adhesively attached; and a plurality of conductive bond wires, said bond wires making electrical connections between said integrated circuit chip and bonding locations on said one layer of conductive trace material, wherein said packaged integrated circuit device has a thickness of less than 2.3 millimeters.

이 특허를 인용한 특허 (185) 인용/피인용 타임라인 분석

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Chen Lung-Tai,TWX ; Chiang Ping-Huang,TWX ; Chou Yu-Kon,TWX ; Chao Chien-Chi,TWX, Structure for semiconductor package for improving the efficiency of spreading heat.
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Hoffman, Paul Robert; Zoba, David Albert, Structures for improving heat dissipation in stacked semiconductor packages.
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Abram M. Castro ; Aaron R. Castro, Substrate for an integrated circuit package.
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Nakayama, Toshinori, Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipment.
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Camenforte, Raymundo M.; Merilo, Dioscoro A.; Chow, Seng Guan, Super thin/super thermal ball grid array package.
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Randolph D. Schueller ; Donald K. Larson, Tape ball grid array with interconnected ground plane.
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Zhao, Sam Ziqun; Khan, Reza-ur Rahman; Law, Edward; Papageorge, Marc, Thermally and electrically enhanced ball grid array package.
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Zhao, Sam Ziqun; Khan, Reaz-ur Rahman; Law, Edward; Papageorge, Marc, Thermally and electrically enhanced ball grid array packaging.
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Manepalli,Rahul N.; Krishnan,Saravanan; Chee,Choong Kooi, Underfilling process in a molded matrix array package using flow front modifying solder resist.
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Shim Il Kwon,KRX ; Heo Young Wook,KRX, Unit printed circuit board carrier frame for ball grid array semiconductor packages and method for fabricating ball grid.
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Shepherd William H. ; Chiang Steve S. ; Xie John Y., Use of conductive particles in a nonconductive body as an integrated circuit antifuse.
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Parvarandeh, Pirooz, Use of device assembly for a generalization of three-dimensional metal interconnect technologies.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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[미국특허] Ball grid array integrated circuit package with thermal conductor 원문보기

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