초록 ▼

A circuit and method for simultaneously steering multiple aligned macroinstructions from an instruction buffer to a decoder that receives and decodes multiple macroinstructions in parallel. A first macroinstruction is supplied to a first decoder by steering a first predetermined number of bytes foll

A circuit and method for simultaneously steering multiple aligned macroinstructions from an instruction buffer to a decoder that receives and decodes multiple macroinstructions in parallel. A first macroinstruction is supplied to a first decoder by steering a first predetermined number of bytes following the first buffer byte. A second macroinstruction is supplied by scanning a first opcode byte vector to locate a first opcode byte, and then steering a second predetermined number of bytes beginning at said first opcode to a second decoder. Operations to locate the first byte of each of the macroinstructions and to steer them to the decoders are accomplished in one cycle. If said macroinstruction cannot be decoded by said second decoder, then it is resteered to the first decoder. Steering and resteering operations continue until all complete macroinstructions within the instruction buffer have been accepted by the decoders.

대표청구항 ▼

A steering method for steering multiple macroinstructions from a block of instruction code in an instruction buffer to a multiple instruction decoder in a processor, said steering method comprising the steps of: a) locating a first non-prefix opcode byte of a first variable length macroinstruction w

A steering method for steering multiple macroinstructions from a block of instruction code in an instruction buffer to a multiple instruction decoder in a processor, said steering method comprising the steps of: a) locating a first non-prefix opcode byte of a first variable length macroinstruction within said instruction buffer; b) steering a first predetermined number of non-prefix bytes beginning with said first non-prefix opcode byte of said first macroinstruction from said instruction buffer to a first decoder, wherein said first predetermined number represents a maximum number of non-prefix bytes permitted in any macroinstruction; c) locating a first non-prefix opcode byte of a second variable length macroinstruction within said instruction buffer; and d) steering a second predetermined number of non-prefix bytes beginning with said first non-prefix opcode byte of said second macroinstruction from said instruction buffer to a second decoder, wherein said first and second predetermined number of non-prefix bytes are steered to said first and second decoders, respectively, substantially simultaneously.