$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Duplicated logic and interconnection system for arbitration among multiple information processors 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/14
출원번호 US-0459456 (1995-06-02)
발명자 / 주소
  • Levenstein Sheldon B. (Rochester MN)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 25  인용 특허 : 34

초록

An information processing network includes multiple processing devices, a main storage memory, and an interface coupling the processing devices to the main storage memory. All processing devices contend for control of the interface on an equal basis, subject to a dynamically shifting sequence of pri

대표청구항

A process for monitoring one of a plurality of processing devices while one of the processing devices controls at least one lock, and for signaling a release of the lock to enable any of said plurality of processing devices to acquire the lock, said process in a data processing network including sai

이 특허에 인용된 특허 (34)

  1. Eggers Thomas W. (95 Matawanakee Trail Littleton MA 01460) Shaffer Stephen J. (Slough Rd. Harvard MA 01451) Warren Richard A. (8501 Alverstone Way Austin TX 78759), Apparatus and method for prohibiting access in a multi-cache data processing system to data signal groups being processe.
  2. Capizzi Giuseppe N. (Brandizzo ITX) Melgara Marcello (Valenza ITX), Arbitration circuitry for deciding access requests from a multiplicity of components.
  3. Liu Lishing (Millwood NY), Cache coherence mechanism based on locking.
  4. Donaldson Darrel D. (Lancaster MA) Howard Mark N. (Issaquah WA) Orbits David A. (Redmond WA) Parchem John M. (Seattle WA) Robinson David M. (Bellevue WA) Williams Douglas (Pepperel MA), Cache coherency protocol for multi processor computer system.
  5. Chan Shiu K. (Poughkeepsie NY) Gerardi John A. (Poughkeepsie NY) McGilvray Bruce L. (Pleasant Valley NY), Cache locking controls in a multiprocessor.
  6. Baird Robert (San Jose CA) Eisenberger George (White Plains NY) Lett Alexander S. (Mahopac NY) Myers James J. (San Francisco CA) Tetzlaff William H. (Mount Kisco NY) Unger Jay G. (Mohegan Lake NY), Concurrency management using version identification of shared data as a supplement to use of locks.
  7. Yount Larry J. (Scottsdale AZ), Data control system for digital automatic flight control system channel with plural dissimilar data processing.
  8. Barlow ; George J., Data processing system having distributed priority network with logic for deactivating information transfer requests.
  9. Quinquis Jean-Paul (rue de Cornic Perros-Guirec FRX 22700), Data transmission system resolving access conflicts between transmitters-receivers to a common bus.
  10. Nielsen Michael J. K. (Palo Alto CA), Distributed arbitration apparatus and method for shared bus.
  11. Ellsworth James G. (St. Paul MN) Wulling Thomas E. (St. Paul MN), Distributed bus arbitration according each bus user the ability to inhibit all new requests to arbitrate the bus, or to.
  12. Wille Ross M. (Sunnyvale CA) Carter Richard J. (Palo Alto CA), Distributed fair arbitration system using separate grant and request lines for providing access to data communication bu.
  13. Cohen Edward I. (Poughkeepsie NY) Pierce Bernard R. (Hyde Park NY), Dynamic queueing method.
  14. Stamm Rebecca L. (Wellesley MA) Bahar Ruth I. (Lincoln NE) Strouble Raymond L. (Charlton MA) Wade Nicholas D. (Folsom CA) Edmondson John H. (Cambridge MA), Ensuring write ordering under writeback cache error conditions.
  15. Lemaire Charles A. (Rochester MN) Luick David A. (Rochester MN), Extended control word decoding.
  16. Cox George W. (Portland OR) Rattner Justin R. (Aloha OR), Interprocessor communication system.
  17. Jippo Akira (Tokyo JPX), Interprocessor communication system in an information processing system enabling communication between execution process.
  18. Nagano ; Genzo ; Nakamura ; Hiroshi ; Sohma ; Yukio, Memory access control system.
  19. Shoens Kurt A. (San Jose CA) Treiber Richard K. (San Jose CA), Method for lock management, page coherency, and asynchronous writing of changed pages to shared external store in a dist.
  20. LaFetra Ross V. (Cupertino CA), Method for maintaining cache coherence in a multiprocessor computer system.
  21. Tetzlaff William H. (Mount Kisco NY) Unger Jay H. (Mohegan Lake NY), Method for minimizing lock processing while ensuring consistency among pages common to local processor caches and a shar.
  22. Pfeifer Randy D. (Warrenville IL), Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system with redundant resources.
  23. Stiffler Jack J. (Concord MA) Karp Richard A. (Bedford MA) Nolan ; Jr. James M. (Holliston MA) Budwey Michael J. (Holliston MA) Wallace David A. (Chelmsford MA), Modular computer system.
  24. Hoffman Roy L. (Pine Island MN) Houdek Merle E. (Rochester MN) Loen Larry W. (Rochester MN) Soltis Frank G. (Rochester MN), Multi-processor task dispatching apparatus.
  25. Hansen, Stanley W.; Whaley, Mark D.; Terleski, John D., Multiprocessor system having distributed priority resolution circuitry.
  26. Mohan Chandrasekaran (San Jose CA) Narang Inderpal S. (Saratoga CA), Non-blocking serialization for removing data from a shared cache.
  27. Keshlear William M. (Richmond TX) Cohen Robert B. (Austin TX), Paged memory management unit which locks translators in translation cache if lock specified in translation table.
  28. Stamm Rebecca L. (Wellesley MA) Wade Nicholas D. (Folsom CA), Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory.
  29. Narayanan C. Murali (Wheaton IL) Zee Benjamin (Oak Park IL), Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements.
  30. Hough Roger E. (Highland NY), Shared and exclusive access control.
  31. Nanba Shinji (Tokyo JPX), Shared memory multiprocessing system & method.
  32. Starr Daniel C. (St. Charles IL), Shared resource locking apparatus.
  33. Taub Daniel M. (Winchester GB2), Synchronization mechanism for a multiprocessing system.
  34. Vander Mey ; James E., System for resolving memory access conflicts among processors and minimizing processor waiting times for access to memo.

이 특허를 인용한 특허 (25)

  1. Juarez, Larry; Qiu, Kenny Nian Gan; Valverde, David Victorino, Computer-implemented multi-resource shared lock.
  2. Juarez, Larry; Qiu, Kenny Nian Gan; Valverde, David Victorino, Computer-implemented multi-resource shared lock.
  3. Mittal Millind, Controlling shared memory access ordering in a multi-processing system using an acquire/release consistency model.
  4. Liu, Zhixin; Cheng, Samuel S.; Liveris, Angelos D.; Xiong, Zixiang, Data encoding and decoding using Slepian-Wolf coded nested quantization to achieve Wyner-Ziv coding.
  5. Liu, Zhixin; Cheng, Samuel S.; Liveris, Angelos D.; Xiong, Zixiang, Data encoding and decoding using Slepian-Wolf coded nested quantization to achieve Wyner-Ziv coding.
  6. Liu,Zhixin; Cheng,Samuel S.; Liveris,Angelos D.; Xiong,Zixiang, Data encoding and decoding using Slepian-Wolf coded nested quantization to achieve Wyner-Ziv coding.
  7. Liu,Zhixin; Cheng,Samuel S.; Liveris,Angelos D.; Xiong,Zixiang, Data encoding and decoding using Slepian-Wolf coded nested quantization to achieve Wyner-Ziv coding.
  8. Saha, Bratin; Adl-Tabatabai, Ali-Reza, Increasing functionality of a reader-writer lock.
  9. Saha, Bratin; Adl-Tabatabai, Ali-Reza, Increasing functionality of a reader-writer lock.
  10. Blumenau Steven M., Lock mechanism.
  11. Harper, III, David T.; Callahan, II, Charles David, Management of ownership control and data movement in shared-memory systems.
  12. Merchant Amit A., Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conf.
  13. Merchant Amit A., Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conf.
  14. Huston, Larry B.; Narad, Charles E., Method and apparatus for serialized mutual exclusion.
  15. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don ; Williams Derek Edward, Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determin.
  16. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don ; Williams Derek Edward, Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priori.
  17. Arimilli Ravi Kumar ; Dodson John Steven ; Lewis Jerry Don ; Williams Derek Edward, Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two.
  18. Cummins Fred A., Method and system for maintaining consistency of shared objects based upon instance variable locking.
  19. Terry Robert Altmayer ; James Alfred Wargnier ; Christopher John Hagan, Multiple processor interface, synchronization, and arbitration scheme using time multiplexed shared memory for real time systems.
  20. Hertwig,Axel; Mehling,Rainer; Koch,Stephan, Multiprocessor array.
  21. Sipple, Ralph E.; Ward, Wayne D., Multiprocessor computer system for processing communal locks employing mid-level caches.
  22. Nakayama, Koichiro; Okamura, Kanna; Tamura, Hiroki, Network system and information processing method.
  23. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.
  24. Miller, Chris D., Resource locking and thread synchronization in a multiprocessor environment.
  25. Hwang,Pei Ching; Scharland,Michael J.; Don,Arieh; Halligan,Kenneth A., Techniques for performing data operations spanning more than two data partitions.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로