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Polysilicon contact stud process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
출원번호 US-0428493 (1995-04-27)
발명자 / 주소
  • Tseng Horng-Huei (Hsin Chu TWX)
출원인 / 주소
  • Vanguard International Semiconductor Corporation (Hsin-Chu TWX 03)
인용정보 피인용 횟수 : 30  인용 특허 : 10

초록

A process for creating a polysilicon contact stud, to connect overlying metallizations, to underlying active device regions in a semiconductor substrate, has been developed. After filling a contact hole with insitu doped polysilicon, and overlying with a titanium film, an anneal cycle is performed t

대표청구항

A method for fabricating a MOSFET device on a semiconductor substrate, using a conductive stud to provide electrical contact between active device elements in the substrate, and an overlying interconnect metallization, comprising the steps of: providing the active device elements in the said semicon

이 특허에 인용된 특허 (10)

  1. Boyd John M. (Woodlawn CAX) Ellul Joseph P. (Nepean CAX) Tay Sing P. (Nepean CAX), Forming resistors for intergrated circuits.
  2. Tanaka Masato (Shiga JPX), Gaseous process for selectively removing silicon nitride film.
  3. Chhabra Navjot (Boise ID) Sandhu Gurtej S. (Boise ID), Metal silicide texturizing technique.
  4. Ku San-Mei (3 Carnelli Ct. Poughkeepsie NY 12603) Perry Kathleen A. (22120 Viscanio Rd. Woodland Hills CA 91364), Method of forming contacts to a semiconductor device.
  5. Beasom James D. (Melbourne FL), Method of making trench conductor and crossunder architecture.
  6. Nakano Eiichi (Tokyo JPX), Method of manufacturing semiconductor device.
  7. Huang Heng-Sheng (Taipei TWX), Polysilicon contact.
  8. Haskell Jacob D. (Palo Alto CA), Process of forming self-aligned interconnects for semiconductor devices.
  9. Yen Yung-Chau (San Jose CA), Silicide contact plug formation technique.
  10. Shepard, Joseph F., Simplified planarization process for polysilicon filled trenches.

이 특허를 인용한 특허 (30)

  1. Yaung Dun-Nian,TWX ; Wuu Shou-Gwo,TWX ; Chao Li-Chih,TWX ; Huang Kuo Ching,TWX, Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits.
  2. Fang Sung-Jen ; Visokay Mark R. ; Khamankar Rajesh B., Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation.
  3. Bromberger,Christoph, Method for structuring a semiconductor device.
  4. Kao Dah-Bin ; Pierce John, Method of fabricating self-aligned contacts and local interconnects in CMOS and BICMOS processes using chemical mechani.
  5. Richard H. Lane ; Fred Fishburn, Method of forming a capacitor container electrode and method of patterning a metal layer by selectively silicizing the electrode or metal layer and removing the silicized portion.
  6. Doan Trung T. ; Wu Zhiqiang ; Li Li, Method of forming a local interconnect between electronic devices on a semiconductor substrate.
  7. Kakehashi Eiichirou,JPX, Method of manufacturing a contact plug.
  8. Farnworth,Warren M.; Brooks,Jerry M., Method of wafer bumping for enabling a stitch wire bond in the absence of discrete bump formation.
  9. Tseng Horng-Huei,TWX, Method to fabricate a polysilicon stud using an oxygen ion implantation procedure.
  10. Ballantine Arne W. ; Chan Kevin K. ; Langdeau Gary L. ; Rice Michael B., Polysilicon structure and process for improving CMOS device performance.
  11. Luan Tran, Selective polysilicon stud growth.
  12. Tran, Luan, Selective polysilicon stud growth.
  13. Tran, Luan, Selective polysilicon stud growth.
  14. Tran, Luan, Selective polysilicon stud growth.
  15. Tran,Luan, Selective polysilicon stud growth.
  16. Tran,Luan, Selective polysilicon stud growth.
  17. Tran,Luan, Selective polysilicon stud growth.
  18. Tran,Luan, Selective polysilicon stud growth.
  19. Tran, Luan, Selective polysilicon stud growth of 6F2 memory cell manufacturing having a convex upper surface profile.
  20. Spring, Kyle, Semiconductor device and process for its manufacture to increase threshold voltage stability.
  21. Yoshida Makoto,JPX ; Kumauchi Takahiro,JPX ; Tadaki Yoshitaka,JPX ; Kajigaya Kazuhiko,JPX ; Aoki Hideo,JPX ; Asano Isamu,JPX, Semiconductor integrated circuit device and process for manufacturing the same.
  22. Yoshida, Makoto; Kumauchi, Takahiro; Tadaki, Yoshitaka; Kajigaya, Kazuhiko; Aoki, Hideo; Asano, Isamu, Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines.
  23. Kato, Hiroki; Serita, Yoichiro, System for managing object in virtual space.
  24. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  25. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  26. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  27. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  28. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  29. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
  30. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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