IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0313728
(1994-09-27)
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발명자
/ 주소 |
- Sharangpani Harshvardhan P. (Santa Clara CA)
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출원인 / 주소 |
- Intel Corporation (Santa Clara CA 02)
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인용정보 |
피인용 횟수 :
10 인용 특허 :
0 |
초록
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A method and apparatus for generating status information about a pipelined processor after the completion of an execution of an instruction. A first storage device stores the current overall status of the processor due to the execution of a plurality of instructions previous to the presently executi
A method and apparatus for generating status information about a pipelined processor after the completion of an execution of an instruction. A first storage device stores the current overall status of the processor due to the execution of a plurality of instructions previous to the presently executing instruction. A second storage device stores an instruction status which represents the status of the processor due to the presently executing instruction alone. Logic generates a new overall status which represents the staus of the processor due to the execution of the present instruction and the previous instructions wherein the new overall status is generated from the instruction status and the current overall status.
대표청구항
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In a microprocessor capable of executing an x87 instruction set and having a pipelined floating point unit with a plurality of stages including a first stage and a last stage, a method of generating an x87 Status Word for an instruction as it completes the last stage of the execution pipeline, said
In a microprocessor capable of executing an x87 instruction set and having a pipelined floating point unit with a plurality of stages including a first stage and a last stage, a method of generating an x87 Status Word for an instruction as it completes the last stage of the execution pipeline, said method comprising the steps of: decoding an instruction into a stream of microvectors or into a single microvector, wherein each of said microvectors comprises a plurality of control fields, wherein a first control field provides control directives for updating a TOS component of the Status Word, a second control field provides boundary information specifying first and last microvectors of said stream of microvectors representing said instruction, wherein if said instruction is decoded into a single microvector said second control field specifies both a first and last microvector, a third control field controls an updating of a plurality of condition code bits P, C1, C0, C2 and C3 of said Status Word and a fourth control field controls the updating of a plurality of components SF, U, 0, Z, D and I of said Status Word; providing in the last stage of the pipeline storage means SW for storing the x87 Status Word representing overall status of the floating point unit due to a plurality of executed instructions, said SW storage means having storage means for each bit of the x87 Status Word, a SW.B storage means for storing a busy bit of the Status Word, storage means SW.C3, SW. C2, SW. C1, SW.CO, for storing the condition code bits C3, C2, C1 and CO, of the Status Word, respectively, a SW.ES storage means for storing an error summary bit of the Status Word, a SW.SF storage means for storing a stack flag bit of the Status Word, a SW.P storage means for storing a status precision bit of the Status Word, a SW.U storage means for storing an underflow exception bit of the Status Word, a SW.O storage means for storing an overflow exception bit of the Status Word, a SW.Z storage means for storing a zero divide bit of the Status Word, a SW.D storage means for storing a denormalized operand bit of the Status Word, a SW.I storage means for storing an invalid operation bit of the Status Word, a SW.TOS storage means for storing a top of stack pointer of said Status Word; providing storage means (TSW) in in a stage prior to said last stage of said pipelined floating point unit said storage means for storing and accumulating status data of said individual microvectors of said instruction, wherein when said last microvector of said instruction is in the second to last stage of the pipeline said accumulated status data representing the status of the floating point unit due to said instruction alone, said TSW storage means having storage means TSW.C3, TSW.C2, TSW.C1, TSW.CO, for storing the condition code bits C3, C2, C1 and CO, respectively, representing the status of the floating point unit due to said instruction alone, a TSW.SF storage means for storing the stack flag bit representing the status of the floating point unit due to said instruction alone, a TSW.P storage means for storing the precision bit representing the status of the floating point unit due to said instruction alone, a TSW.U storage means for storing the underflow exception bit representing the status of the floating point unit due to said instruction alone, a TSW.0 storage means for storing the overflow bit representing the status of the floating point unit due to said instruction alone, a TSW.Z storage means for storing the zero divide bit representing the status of the floating point unit due to said instruction alone, a TSW.D storage means for storing the denormalized operand bit representing the status of the floating point unit due to said instruction alone, a TSW.I storage means for storing the invalid operation bit representing the status of the floating point unit due to said instruction alone, a TSW.TOS storage means for storing the present top of stack pointer due to said instruction; associating a valid bit VP with said TSW.P storage means, associating a valid bit VC1 with said TSW.C1 storage means and associating a valid bit Vccc with the group of TSW.C0, TSW.C2 and TSW.C3 storage means wherein said valid bits indicate when said associative storage means contains valid data; generating with each microvector of said instruction a TOS value, wherein said TOS value is generated from said first control field of said microvector, and staging down said TOS value, along with said microvector which generated said TOS value, to said TSW.TOS storage means; clearing said TSW.B, TSW.C3, TSW.C2, TSW.C1, TSW.C0, TSW.ES, TSW.SF, TSW.P, TSW.U, TSW.O, TSW.Z, TSW.D and TSW.I storage means each time a first microvector enters the second to last stage of the pipeline; updating with each microvector of said instruction a prespecified group of said TSW.C0, TSW.C1, TSW.C2, TSW.C3 and TSW.P storage means and setting said associated valid bits of those storage means which have been updated, said updated group specified by said third control field of said microvector; updating with each microvector of said instruction said TSW.SF, TSW.U, TSW.0, TSW.Z, TSW.D and TSW.I storage means according to said fourth control field of said microvectors; and generating when said last microvector is in the last stage of the pipeline a new Status Word from said accumulated status stored in said TSW storage means and from the current Status Word presently stored in said SW storage means said new Status Word providing the overall status of the processor after execution of said instruction.
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