[특허]Apparatus and method for detecting defects in insulative layers of MOS active devices

[미국특허] Apparatus and method for detecting defects in insulative layers of MOS active devices 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-023/58
출원번호	US-0224947 (1994-04-08)
발명자 / 주소	Krishnan Srikanth (Richardson TX) McKee Jeffrey A. (Grapevine TX)
출원인 / 주소	Texas Instruments Incorporated (Dallas TX 02)
인용정보	피인용 횟수 : 12 인용 특허 : 4

초록 ▼

A technique for quantifying the effect of plasma/etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18. Electrical characterization is performed on modified MOS capacitor 40 yielding information about damage to the oxide in peripheral region 24 caused by the plasma etch. Modified MOS capacitor 40 can be used to compare plasma chemistries, detect oxide trenching, detect etchant loading and determine the effect of process hardware changes, for example. It can especially account for oxide loss in tight geometry features and in regimes where optical measurement techniques are unreliable.

대표청구항 ▼

An MMOS capacitor formed similarly to an MOS transistor, the transistor being of the type having a substrate, a gate dielectric and a gate, the MMOS capacitor comprising: a second substrate; a dielectric on the second substrate, said dielectric being similar to the gate dielectric; a conductive plate on the dielectric, a portion of the dielectric immediately surrounding the plate being partially etched due to the formation of the plate; a conductive sidewall which is electrically continuous with the conductive plate and which overlies the partially etched portion of the dielectric, such that the conductive plate and the conductive sidewall overly a portion of the second substrate which has a uniform impurity concentration; and whereby the electrical characteristics of the MMOS capacitor provides an indication of the electrical characteristics of the transistor.

이 특허에 인용된 특허 (4) 인용/피인용 타임라인 분석

Ariizumi, Shoji; Segawa, Makoto, Charge pump substrate bias with antiparasitic guard ring.
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Endo Koichi (Tokyo JPX), MIS type capacitor having reduced change in capacitance when biased in forward and reverse directions.
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Sanchez Julian J. B. (Mesa AZ), Self-aligned overlap MOSFET and method of fabrication.
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Kinoshita Mitsuya (Hyogo JPX) Okamoto Tatsuo (Hyogo JPX) Arima Hideaki (Hyogo JPX) Hachisuka Atsushi (Hyogo JPX), Semiconductor memory device having cylindrical capacitor and manufacturing method thereof.
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이 특허를 인용한 특허 (12) 인용/피인용 타임라인 분석

Howland, William H., Apparatus and method for determining electrical properties of a semiconductor wafer.
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Krishnan,Srinath; En,William George, Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies.
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Chen, Bor-Cheng; Tai, Yu-Feng, Early response to plasma/charging damage by special pattern design of active region.
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Chen, Bor-Cheng; Tai, Yu-Feng, Early response to plasma/charging damage by special pattern design of active region.
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Nelson Mark Michael ; Deshmukh Subhash Madhukar, Electrical diagnostic technique for silicon plasma-etch induced damage characterization.
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Nelson Mark Michael ; Deshmukh Subhash Madhukar, Method for detecting and characterizing plasma-etch induced damage in an integrated circuit.
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Cho,Min hee; Kim,Ji young, Method for forming gate of semiconductor device.
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Shiue Ruey-Yun,TWX ; Hsu Sung-Mu,TWX, Plasma damage monitor.
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Brooks Daniel S. ; Chapman Phillip F. ; Cronin John E. ; Wistrom Richard E., Semiconductor and method of fabricating.
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Daniel S. Brooks ; Phillip F. Chapman ; John E. Cronin ; Richard E. Wistrom, Semiconductor and method of fabricating.
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Kiehlbauch, Mark, Semiconductor constructions.
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Daubenspeck, Timothy H.; Gambino, Jeffrey P.; Muzzy, Christopher D.; Sauter, Wolfgang, Semiconductor test wafer and methods for use thereof.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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[미국특허] Apparatus and method for detecting defects in insulative layers of MOS active devices 원문보기