초록 ▼

A new method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device is described. Semiconductor device structures are formed in and on a semiconductor substrate. A dielectric layer is deposited overlying the semiconductor device structu

A new method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device is described. Semiconductor device structures are formed in and on a semiconductor substrate. A dielectric layer is deposited overlying the semiconductor device structures. The dielectric layer is covered with a photoresist mask and partially etched into to form first openings of a first width wherein the first openings do not contact the underlying semiconductor device structures. An oxide layer is deposited over the dielectric layer and within the first openings whereby second openings are formed having a second width smaller than the first width. The oxide layer is etched away whereby the second openings are extended through the dielectric layer to the underlying semiconductor device structures to form small contact openings having the second width and whereby the dielectric layer is planarized. A conducting layer is deposited and patterned to complete the formation of the small contacts and planarized dielectric layer in the fabrication of an integrated circuit device.

대표청구항 ▼

A method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device comprising: forming semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures;

A method for forming small contacts and for planarizing the dielectric layer in the fabrication of an integrated circuit device comprising: forming semiconductor device structures in and on a semiconductor substrate; depositing a first dielectric layer overlying said semiconductor device structures; covering said first dielectric layer with a photoresist mask and partially etching into said first dielectric layer to form first openings of a first width wherein said first openings do not contact said underlying semiconductor device structures; depositing a second dielectric layer over said first dielectric layer and within said first openings whereby second openings are formed having a second width smaller than said first width; etching away said second dielectric layer whereby said second openings are extended downward through said first dielectric layer to said underlying semiconductor device structures to form small contact openings having said second width and whereby said first dielectric layer is planarized; and depositing and patterning a conducting layer to complete the formation of said small contacts and said planarized dielectric layer in the fabrication of said integrated circuit device.