초록 ▼

A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and

A wireless alarm system using spread spectrum transmitters, fast frequency shift keying, spread spectrum receivers and computer with a display. The spread spectrum transmitter includes an oscillator coupled to a microprocessor with chip code generation means, preamble register, address register and data register. The spread spectrum receiver acquires synchronization of the spread spectrum signal using a microprocessor coupled to the quieting, signal strength or baseband output of the receiver, with a two step algorithm. The steps comprise achieving a coarse lock and a fine lock to the spread spectrum signal.

대표청구항 ▼

A spread spectrum chip code synchronization apparatus, coupled to a baseband output of a receiver, the spread spectrum chip code synchronization apparatus comprising: means coupled to the baseband output of said receiver for sampling and digitizing a plurality of analog baseband signals, from the ba

A spread spectrum chip code synchronization apparatus, coupled to a baseband output of a receiver, the spread spectrum chip code synchronization apparatus comprising: means coupled to the baseband output of said receiver for sampling and digitizing a plurality of analog baseband signals, from the baseband output of said receiver, as a plurality of data signals, wherein each of the analog baseband signals is sampled and digitized as one of the plurality of data signals during one chip time; register means, including a plurality of shift registers, said register means coupled to said sampling and digitizing means, for shifting the plurality of data signals sequentially through the plurality of shift registers; and means coupled to said register means for adding in parallel each of the plurality of data signals stored in said plurality of shift registers with a respective one of a plurality of weights, as a respective result, and for adding sequentially the results as a correlation sum for attaining chip code synchronization.