초록 ▼

A configurable hardware system for implementing an algorithmic language program, including at least two programmable logic devices (PLD), a private hardware resource connectible to one PLD, and a programmable connection between PLDs, all of which may be configured as a module or distributed processi

A configurable hardware system for implementing an algorithmic language program, including at least two programmable logic devices (PLD), a private hardware resource connectible to one PLD, and a programmable connection between PLDs, all of which may be configured as a module or distributed processing units (DPU). The private hardware resource may include a serial processing device such as a DSP, a PLD, a memory device, or a CPU. An extensible processing unit (EPU) can be built out of multiple DPUs, each connected to other modules by one or more of several buses. An N-bus (neighbor bus) connects a module to its nearest neighbor, an M-bus (module bus) connects a group of modules, and an H-bus (host bus) connects a module to a host CPU. The invention also includes a method of translating source code in an algorithmic language into a configuration file for implementation on one or more DPUs. The method includes four sequential phases of translation, a tokenizing phase, a logical mapping phase, a logic optimization phase, and a device specific mapping phase.

대표청구항 ▼

A configurable hardware module comprising: a first and a second programmable logic device (PLD), each said PLD comprising a plurality of programmable pins for connection to one or more devices and also comprising internal programmable interconnect and configurable logic, at least one of said program

A configurable hardware module comprising: a first and a second programmable logic device (PLD), each said PLD comprising a plurality of programmable pins for connection to one or more devices and also comprising internal programmable interconnect and configurable logic, at least one of said programmable pins connectible through said programmable interconnect to said configurable logic; a configurable bus directly connecting said first PLD and said second PLD, said configurable bus comprising a plurality of configurable bus lines, each of said configurable bus lines comprising a connection between a programmable pin on said first PLD and a corresponding programmable pin on said second PLD; a private hardware resource directly connectible to said second PLD but not to said first PLD; and a means for configuring said first PLD and said second PLD, whereby at least one of said configurable bus lines can be connected at a first time for communication between first configurable logic in said first PLD and first configurable logic in said second PLD to communicate a first signal and connected at a second time for communication between second configurable logic in said first PLD and second configurable logic in said second PLD to communicate a second signal, where at least one of said first signal and said second signal or said first and second configurable logic in said first PLD or said first and second configurable logic in said second PLD are not the same.