$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Molded plastic semiconductor package including heat spreader 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/28
출원번호 US-0276381 (1994-07-18)
발명자 / 주소
  • Mahulikar Deepak (Madison CT) Tyler Derek E. (Cheshire CT) Braden Jeffrey S. (Livermore CA) Popplewell James M. (Guilford CT)
출원인 / 주소
  • Olin Corporation (Manteca CA 02)
인용정보 피인용 횟수 : 246  인용 특허 : 37

초록

There is provided a molded plastic electronic package having improved thermal dissipation. A thermal dissipator, such as a heat spreader or a heat slug is partially encapsulated in the molding resin. The thermal dissipator has a density less than that of copper and a coefficient of thermal conductiv

대표청구항

A semiconductor package, comprising: at least one semiconductor device bonded to a first side of a thermal dissipator; said thermal dissipator having a first side and an opposing second side and being selected from the group consisting of aluminum, titanium, zinc, magnesium and alloys thereof with a

이 특허에 인용된 특허 (37)

  1. Wurst Stephen G. (Orange CA) Matsunaga Kaori E. (Hawthorne CA), Aircraft vision augmentation system with adjustable external mirror and cockpit mirror.
  2. Mahulikar Deepak (Meriden CT) Popplewell James M. (Guilford CT), Aluminum alloy semiconductor packages.
  3. Winton, Robert A.; Christie, Eugene F., Aluminum-fluoropolymer laminate.
  4. Itoh Yoshiaki (Hyogo JPX) Odani Yusuke (Hyogo JPX) Akechi Kiyoaki (Hyogo JPX) Kuroishi Nobuhito (Hyogo JPX), Aluminum-silicon alloy heatsink for semiconductor devices.
  5. Pryor Michael J. (Woodbridge CT) Shapiro Eugene (Hamden CT) Mahulikar Deepak (Meriden CT), Cermet substrate with spinel adhesion component.
  6. Lin Lifun (Waltham MA) Chao Chung-Yao (Waltham MA), Chromium-zinc anti-tarnish coating on copper foil.
  7. Butt Sheldon H. (Godfrey IL), Clad metal lead frame substrates.
  8. Rosenfeld Aron M. (Kingston CAX) Smits Paul (Kingston CAX), Color change devices incorporating thin anodic films.
  9. Eerkes Thijs (Oakville CAX) Diaz Carlos M. (Mississauga CAX) Bell James A. E. (Oakville CAX), Composite structure.
  10. Belopolsky Yakov (Hockessin DE), Electronic assembly with optimum heat dissipation.
  11. SinghDeo Narendra N. (New Haven CT) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL), Electronic packaging of components incorporating a ceramic-glass-metal composite.
  12. Kushida Hachiro (Tanashi JPX), External member for a watch.
  13. Alvarez Juan M. (Medfield MA) Breit Henry F. (Attleboro MA) Levy Steven E. (Plainville MA) Hingorany Premkumar R. (Foxboro MA), Heat dissipating member for mounting a semiconductor device and electrical circuit unit incorporating the member.
  14. Spaight ; Ronald Neil, Heat transfer mechanism for integrated circuit package.
  15. Lin Lifun (Hamden CT), Hermetic cerglass and cermet electronic packages.
  16. Mahulikar Deepak (Meriden CT) Crane Jacob (Woodbridge CT) Braden Jeffrey S. (Milpitas CA), Kit for the assembly of a metal electronic package.
  17. Mahulikar Deepak (Madison CT) Fister Julius C. (Hamden CT) Violette Gerald N. (Hamden CT), Lead frame having polymer coated surface portions.
  18. Butt Sheldon H. (Godfrey IL), Low thermal expansivity and high thermal conductivity substrate.
  19. Shirai Hideaki (Amagasaki JPX) Chiba Kimio (Amagasaki JPX) Okawa Koji (Amagasaki JPX) Ishibashi Hiroshi (Amagasaki JPX) Ishii Akihiro (Amagasaki JPX) Itoh Hirotaka (Amagasaki JPX) Kuzushita Hirokazu , Metal cored board and method for manufacturing same.
  20. Braden Jeffrey S. (Milpitas CA), Method for housing a tape-bonded electronic device and the package employed.
  21. Pryor Michael J. (Woodbridge CT), Method for making multi-layer and pin grid arrays.
  22. Tateno Kenichi (Shiga JPX) Yokozawa Masami (Kyoto JPX) Fujii Hiroyuki (Osaka JPX) Nishikawa Mikio (Kyoto JPX) Katoh Michio (Osaka JPX) Wada Fujio (Kyoto JPX), Method for manufacturing a plastic encapsulated semiconductor device and a lead frame therefor.
  23. Hiroshi Okuaki (Tokyo JPX), Method of manufacturing eprom device.
  24. Gohausen ; Hans Jurgen ; Kirchhoff ; Winfried ; Lindener ; Jurgen, Method of sealing oxidized aluminum surfaces with aqueous solutions of polycarboxylic acids.
  25. Mahulikar Deepak (Madison CT) Braden Jeffrey S. (Livermore CA) Chen Szuchain F. (Orange CT), Molded plastic semiconductor package including an aluminum alloy heat spreader.
  26. Mahulikar Deepak (Meriden CT), Process for manufacturing a metal pin grid array package.
  27. Hornbostel Lloyd (Beloit WI) Butrymowicz Dale (Janesville WI), Process for preparing a part for color anodization.
  28. Pasqualoni Anthony M. (Hamden CT) Mahulikar Deepak (Meriden CT) Jalota Satish K. (Wallingford CT) Brock Andrew J. (Cheshire CT), Process for producing black integrally colored anodized aluminum components.
  29. Chen Szuchain (Orange CT) Yukov Nina (Orange CT), Protective coating having adhesion improving characteristics.
  30. Komatsubara Toshio (Tokyo JPX) Tagata Tsutomu (Tokyo JPX) Matsuo Mamoru (Tokyo JPX), Rolled aluminum alloy adapted for superplastic forming and method for making.
  31. Butt Sheldon H. (Godfrey IL), Semiconductor casing.
  32. Suzuki Akira (Ohme JPX) Tanaka Hideki (Koganei JPX) Murakami Gen (Machida JPX), Semiconductor device and method of manufacturing thereof.
  33. Sawaya Hiromichi (Kanagawa JPX), Semiconductor device having insulating substrate adhered to conductive substrate.
  34. Crane Jacob (Woodbridge CT) Johnson Barry C. (Tucson AZ) Mahulikar Deepak (Meriden CT) Butt Sheldon H. (Godfrey IL), Semiconductor package.
  35. Sukonnik Israil M. (Plainville MA) Forster James A. (Barrington RI) Breit Henry F. (Attleboro MA) Raphanella Gary A. (South Easton MA), Substrate for an electrical circuit system and a circuit system using that substrate.
  36. Breedis John F. (Trumbull CT) Muench George J. (Hamden CT) Mahulikar Deepak (Madison CT), Surface modified copper alloys.
  37. Medeiros ; III Manuel (Acushnet MA) Greenspan Jay S. (South Dartmouth MA), Surface mount device with high thermal conductivity.

이 특허를 인용한 특허 (246)

  1. Golan, Gad; Galperin, Yuly, Adhesive composition for electrical PTC heating device.
  2. Yoshida, Hideo; Abe, Kentaro; Sakon, Kiyohito, Anodic oxidation method and production for titanium oxide coating and method of supporting catalyst.
  3. Gard, Leo; Wefers, Karl, Apparatus for electrical isolation of metallic hardware.
  4. Fuller, Jr., James W.; Knight, Jeffrey A., Article exhibiting enhanced adhesion between a dielectric substrate and heat spreader and method.
  5. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Backside warpage control structure and fabrication method.
  6. d'Estries,Maximilien, Cavity case with clip/plug for use on multi-media card.
  7. Gary L. Swiss ; Angel O. Alvarez, Cavity semiconductor package with exposed leads and die pad.
  8. McLellan, Neil; Wagenhoffer, Katherine; Lin, Geraldine Tsui Yee; Kirloskar, Mohan, Cavity-type integrated circuit package.
  9. Miks, Jeffrey Alan; Roman, David; Miranda, John A., Compact flash memory card with clamshell leadframe.
  10. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode.
  11. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  12. Do, Won Chul; Ko, Yong Jae, Conductive pad on protruding through electrode semiconductor device.
  13. Mertol Atila, Conformal diamond coating for thermal improvement of electronic packages.
  14. Davis, Terry W.; Son, Sun Jin, Conformal shield on punch QFN semiconductor package.
  15. Knowles, Timothy R.; Seaman, Christopher L., Dendritic fiber material.
  16. Knowles,Timothy R.; Seaman,Christopher L., Dendritic fiber material.
  17. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  18. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  19. Berry, Christopher John; Huemoeller, Ronald Patrick; Hiner, David Jon, Direct-write wafer level chip scale package.
  20. Miks,Jeffrey A.; Shis,Jung Chun, Drop resistant bumpers for fully molded memory cards.
  21. Berry, Christopher J., Dual laminate package structure with embedded elements.
  22. Nishii Kota,JPX ; Kimura Kouichi,JPX ; Ishizuki Masanobu,JPX ; Adachi Katsura,JPX ; Uchida Hiroki,JPX, Electronic apparatus, housing for electronic apparatus and housing manufacturing method.
  23. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Electronic component package comprising fan-out and fan-in traces.
  24. Fan,Chun Ho; Tsang,Kwok Cheung, Electronic components such as thin array plastic packages and process for fabricating same.
  25. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  26. Huemoeller, Ronald Patrick; Kelly, Michael; Hiner, David Jon, Embedded component package and fabrication method.
  27. Huemoeller, Ronald Patrick; Rusli, Sukianto; Hiner, David J., Embedded electronic component package.
  28. Huemoeller, Ronald P.; Rusli, Sukianto; Hiner, David Jon, Embedded electronic component package fabrication method.
  29. Sheridan,Richard Peter; Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto, Embedded leadframe semiconductor package.
  30. Callen Brian William,CAX ; Timsit Roland Sion,CAX, Enhanced emissivity electrical connector.
  31. Berry, Christopher J.; Scanlan, Christopher M.; Faheem, Faheem F., Etch singulated semiconductor package.
  32. Berry,Christopher J.; Scanlan,Christopher M.; Faheem,Faheem F., Etch singulated semiconductor package.
  33. Ramirez German ; Pedron ; Jr. Serafin Padilla, Exposed heat spreader with seal ring.
  34. Foster, Donald C., Exposed lead QFP package fabricated through the use of a partial saw process.
  35. Foster,Donald C., Exposed lead QFP package fabricated through the use of a partial saw process.
  36. Foster,Donald Craig, Exposed lead interposer leadframe package.
  37. Lin, Pang-Chun; Li, Chun-Yuan; Tang, Fu-Di; Huang, Chien-Ping; Ke, Chun-Chi, Fabrication method of semiconductor package having electrical connecting structures.
  38. Scanlan, Christopher M.; St. Amand, Roger D.; Kim, Jae Dong, Fan out build up substrate stackable package and method.
  39. Davis,Terry W., Fan-in leadframe semiconductor package.
  40. Knowles,Timothy R.; Seaman,Christopher L., Fiber adhesive material.
  41. Choi, YeonHo; Olson, Timothy L., Flat semiconductor package with half package molding.
  42. Hu,Chuan; Lu,Daoqiang, Fluxless die-to-heat spreader bonding using thermal interface material.
  43. Zwenger,Curtis Michael; Miks,Jeffrey Alan, Front edge chamfer feature for fully-molded memory cards.
  44. Zwenger, Curtis M.; Guerrero, Raul M.; Kang, Dae Byoung; Park, Chul Woo, Fully-molded leadframe stand-off feature.
  45. Jech David E. ; Frazier Jordan P. ; Sworden Richard H. ; Sepulveda Juan L., Functionally graded metal substrates and process for making same.
  46. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  47. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  48. Suwa, Yoriyuki; Kawamura, Kenji, Heat radiating component and semiconductor package having the same.
  49. Murayama, Kei; Suganuma, Shigeaki; Kitajima, Masakuni; Matsuki, Ryuichi; Miyajima, Hiroyuki, Heat radiation component and semiconductor package including same.
  50. Degner, Brett W.; Augenbergs, Peteris K.; Liang, Frank; Heresztyn, Amaury J.; Mathew, Dinesh; Wilson, Thomas W., Heat removal in compact computing systems.
  51. Ishikawa,Takahiro; Shinkai,Masayuki; Miyahara,Makoto; Ishikawa,Shuhei; Nakayama,Nobuaki; Yasui,Seiji, Heat spreader module.
  52. Ishikawa,Shuhei, Heat spreader module and method of manufacturing same.
  53. Poinelli Renato,ITX ; Corno Marziano,ITX, Heat-dissipating and supporting structure for a plastic package with a fully insulated heat sink for an electronic devi.
  54. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  55. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  56. Lee, Chang Deok; Na, Do Hyun, Increased I/O semiconductor package and method of making same.
  57. Yang,Sung Jin; Moon,Doo Hwan; Shin,Won Dai, Increased capacity leadframe and semiconductor package using the same.
  58. Kim, Jae Yoon; Kim, Gi Jeong; Moon, Myung Soo, Increased capacity semiconductor package.
  59. Fusaro,James M.; Darveaux,Robert F.; Rodriguez,Pablo, Integrated circuit device packages and substrates for making the packages.
  60. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  61. Kirloskar,Mohan; Wagenhoffer,Katherine; Higgins, III,Leo M., Integrated circuit package and method for fabricating same.
  62. Glenn, Thomas P., Integrated circuit package and method of making the same.
  63. Glenn, Thomas P., Integrated circuit package and method of making the same.
  64. Glenn, Thomas P., Integrated circuit package and method of making the same.
  65. Glenn, Thomas P., Integrated circuit package and method of making the same.
  66. Glenn, Thomas P., Integrated circuit package and method of making the same.
  67. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package and process for fabricating the same.
  68. Lin, Geraldine Tsui Yee; de Munnik, Walter; Kwan, Kin Pui; Lau, Wing Him; Tsang, Kwok Cheung; Fan, Chun Ho; McLellan, Neil, Integrated circuit package having a plurality of spaced apart pad portions.
  69. Shim, Il Kwon; Chow, Seng Guan; Punzalan, Jeffrey D.; Han, Byung Joon; Ramakrishna, Kambhampati, Integrated circuit package to package stacking system.
  70. McLellan,Neil; Lin,Geraldine Tsui Yee; Fan,Chun Ho; Kirloskar,Mohan; Varga,Ed A., Integrated circuit package with partially exposed contact pads and process for fabricating the same.
  71. Rumer, Christopher L.; Houle, Sabina J.; Jayaraman, Saikumar; Koning, Paul A.; Dani, Ashay, Integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and method of making an electronic assembly.
  72. Rumer,Christopher L.; Houle,Sabina J.; Jayaraman,Saikumar; Koning,Paul A.; Dani,Ashay, Integrated heat spreader, heat sink or heat pipe with pre-attached phase change thermal interface material and method of making an electronic assembly.
  73. Fuentes, Ruben; Dunlap, Brett, Integrated passive device structure and method.
  74. Lee, Hyung Ju, Lead frame for semiconductor package.
  75. Lee, Hyung Ju, Lead frame for semiconductor package.
  76. Lee,Hyung Ju, Lead frame for semiconductor package.
  77. Fogelson, Harry J.; Bancod, Ludovico Estrada; Syed, Ahmer; Davis, Terry; Palasi, Primitivo A.; Anderson, William M., Lead frame with plated end leads.
  78. Miks,Jeffrey Alan; Kaskoun,Kenneth; Liebhard,Markus; Foster,Donald Craig; Hoffman,Paul Robert; Bertholio,Frederic, Lead-frame method and assembly for interconnecting circuits within a circuit module.
  79. Bogner, Georg; Brunner, Herbert; Hiegler, Michael; Waitl, Günter, Leadframe and housing for radiation-emitting component, radiation-emitting component, and a method for producing the component.
  80. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
  81. Ahn, Byung Hoon; Ku, Jae Hun; Chung, Young Suk; Ko, Suk Gu; Jang, Sung Sik; Choi, Young Nam; Do, Won Chul, Leadframe and semiconductor package made using the leadframe.
  82. Ahn,Byung Hoon; Ku,Jae Hun; Chung,Young Suk; Ko,Suk Gu; Jang,Sung Sik; Choi,Young Nam; Do,Won Chul, Leadframe and semiconductor package made using the leadframe.
  83. Lee,Tae Heon; Chung,Young Suk; Seo,Mu Hwan, Leadframe and semiconductor package with improved solder joint strength.
  84. Miks,Jeffrey Alan; Zwenger,Curtis Michael; Co,Ziehl Neelsen L., Leadframe based memory card.
  85. Lee, Hyung Ju, Leadframe for semiconductor package.
  86. Yee,Jae Hak; Chung,Young Suk; Lee,Jae Jin; Davis,Terry; Han,Chung Suk; Ku,Jae Hun; Kwak,Jae Sung; Ryu,Sang Hyun, Leadframe having lead locks to secure leads to encapsulant.
  87. Lee, Choon Heung; Jang, Sung Sik; Yoo, Su Yol, Leadframe including corner leads and semiconductor package using same.
  88. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
  89. Edwards, Keith M.; Gillett, Blake A., Leadframe package for semiconductor devices.
  90. Bancod,Ludovico E.; Alabin,Leocadio M.; Davis,Terry W.; Kent,Ian, Leadframe strip having enhanced testability.
  91. Kuo, Bob Shih Wei; Nickelsen, Jr., John Merrill; Olson, Timothy L., Leadframe structure for concentrated photovoltaic receiver package.
  92. Kim,Gi Jeong; Kim,Jin Han; Oh,Jin Seok, Leadframe type semiconductor package having reduced inductance and its manufacturing method.
  93. Kwan,Kin Pui; Lau,Wing Him; Tsang,Kwok Cheung; Fan,Chun Ho; McLellan,Neil, Leadless plastic chip carrier.
  94. Fan,Chun Ho; Lin,Tsui Yee; Lau,Ping Sheung, Leadless plastic chip carrier and method of fabricating same.
  95. Fan, Chun Ho; Kwan, Kin Pul; Wong, Hoi Chi; McLellan, Neil, Leadless plastic chip carrier with contact standoff.
  96. Gillett, Blake A.; Crowley, Sean T.; Boland, Bradley D.; Edwards, Keith M., Making two lead surface mounting high power microleadframe semiconductor packages.
  97. Yang,Sung Jin; Moon,Doo Hwan, Manufacturing method for leadframe and for semiconductor package using the leadframe.
  98. Fehr Gerald K., Method for encapsulating IC packages with diamond substrate.
  99. Davis,Terry W., Method for fabricating a fan-in leadframe semiconductor package.
  100. Fan,Chun Ho; Kirloskar,Mohan, Method of fabricating a leadless plastic chip carrier.
  101. Dunlap, Brett Arnold, Method of forming a plurality of electronic component packages.
  102. Edwards,Keith M.; Gillett,Blake A., Method of making a leadframe for semiconductor devices.
  103. Glenn, Thomas P., Method of making an integrated circuit package.
  104. Glenn, Thomas P., Method of making an integrated circuit package.
  105. Glenn,Thomas P., Method of making an integrated circuit package.
  106. Glenn,Thomas P., Method of making an integrated circuit package.
  107. Glenn,Thomas P., Method of making an integrated circuit package.
  108. Chien Ping Huang TW; Tzong-Da Ho TW; Cheng-Hsu Hsiao TW, Method of making semiconductor package with heat spreader.
  109. Huang,Chien Ping; Ho,Tzong Da; Hsiao,Cheng Hsu, Method of making semiconductor package with heat spreader.
  110. Zaderej, Victor; O'Connor, Kevin; Manlapaz, Charlie; Hagan, Timothy; Ramey, Samuel C., Method of manufacturing an interconnect device which forms a heat sink and electrical connections between a heat generating device and a power source.
  111. Tanaka,Katsufumi; Kinoshita,Kyoichi; Sugiyama,Tomohei; Kono,Eiji, Method of producing base plate circuit board, base plate for circuit board, and circuit board using the base plate.
  112. Thomas P. Glenn ; Scott J. Jewler ; David Roman ; J. H. Yee KR; D. H. Moon KR, Methods for moding a leadframe in plastic integrated circuit devices.
  113. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  114. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  115. Paschkewitz, John S.; Johnson, David M., Molded plastic objects having an integrated heat spreader and methods of manufacture of same.
  116. Paschkewitz, John S.; Johnson, David M., Molded plastic objects having an integrated heat spreader and methods of manufacture of same.
  117. Glenn, Thomas P.; Webster, Steven; Hollaway, Roy D., Mounting for a package containing a chip.
  118. Glenn, Thomas P.; Webster, Steven; Hollaway, Roy D., Mounting for a package containing a chip.
  119. Ramos, Mary Jean Bajacan; San Antonio, Romarico Santos; Subagio, Anang, No lead package with heat spreader.
  120. Sorgo, Miksa de, Non-electrically conductive thermal dissipator for electronic components.
  121. Bancod, Ludovico; Dela Cruz, Gregorio G.; Canoy, Fidelyn R.; Alabin, Leocadio M., Offset etched corner leads for semiconductor package.
  122. Lye,Poh Huat; Leong,Ak Wing, Optical integrated circuit package.
  123. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  124. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  125. Kang, Dae Byoung; Yang, Sung Jin; Ok, Jung Tae; Kim, Jae Dong, Package in package semiconductor device.
  126. Hwang, Chan Ha; Sohn, Eun Sook; Choi, Ho; Kim, Byong Jin; Yu, Ji Yeon; Lee, Min Woo, Package in package semiconductor device with film over wire.
  127. Camacho, Zigmund Ramirez; Bathan, Henry Descalzo; Tay, Lionel Chien Hui; Punzalan, Jeffrey D., Packaging system with hollow package and method for the same.
  128. Glenn, Thomas P.; Jewler, Scott J.; Roman, David; Yee, Jae Hak; Moon, Doo Hwan, Plastic integrated circuit device package and method for making the package.
  129. Glenn, Thomas P., Plastic integrated circuit package and leadframe for making the package.
  130. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
  131. Glenn,Thomas P., Plastic integrated circuit package and method and leadframe for making the package.
  132. Thomas P. Glenn, Plastic integrated circuit package and method and leadframe for making the package.
  133. Crowley, Sean T.; Anderson, William M.; Boland, Bradley D.; Bergman, Eelco, Power semiconductor package with strap.
  134. Gao, Wei, Powerpack laser diode assemblies.
  135. Miks, Jeffrey Alan; Schoonejongen, Ronald James, Pre-molded leadframe.
  136. Fogelson, Harry J.; Bancod, Ludovico E.; dela Cruz, Gregorio G.; Palasi, Primitivo A.; Anderson, William M.; Syed, Ahmer, Reduced copper lead frame for saw-singulated chip package.
  137. Kim, Bong Chan; Kim, Do Hyung; Hwang, Chan Ha; Lee, Min Woo; Sohn, Eun Sook; Kang, Won Joon, Reduced profile stackable semiconductor package.
  138. Paek, Jong Sik, Reduced size semiconductor package with stacked dies.
  139. Kim, Bong Chan; Na, Jae Young; Song, Jae Kyu, Reduced size stacked semiconductor package and method of making the same.
  140. Miks, Jeffrey Alan; Miranda, John Armando, Reinforced lead-frame assembly for interconnecting circuits within a circuit module.
  141. Kazuaki Sorimachi JP; Masayoshi Kikuchi JP, Resin sealed semiconductor device utilizing a clad material heat sink.
  142. Kuroyama, Masumi; Ishikawa, Tomonori; Kato, Kazuo; Sasaki, Yaeko; Miura, Shuhei; Nakamura, Masayuki; Sato, Setsuko, Resin-metal bonded body and method for producing the same.
  143. Hu, Tom; Davis, Terry W.; Bancod, Ludovico E.; Shin, Won Dai, Saw and etch singulation method for a chip package.
  144. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
  145. Mclellan Neil,HKX ; Fan Nelson,HKX, Saw-singulated leadless plastic chip carrier.
  146. Kim, Sang Won; Jung, Boo Yang; Kim, Sung Kyu; Yoo, Min; Lee, Seung Jae, Semiconductor device and fabricating method thereof.
  147. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device and manufacturing method thereof.
  148. Udrea, Florin; Amaratunga, Gehan Anil Joseph, Semiconductor device and method of forming a semiconductor device.
  149. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  150. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  151. Kim, Gwang Ho; Kim, Jin Seong; Park, Dong Joo; Kang, Dae Byoung, Semiconductor device including increased capacity leadframe.
  152. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  153. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  154. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands.
  155. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  156. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  157. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  158. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  159. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  160. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  161. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  162. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  163. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
  164. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  165. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  166. Peter Steimer CH; Alexander Stuck CH; Hansruedi Zeller CH; Raymond Zehringer CH, Semiconductor module.
  167. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
  168. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
  169. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
  170. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
  171. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
  172. Jae Hak Yee KR; Young Suk Chung KR; Jae Jin Lee KR; Terry Davis ; Chung Suk Han KR; Jae Hun Ku KR; Jae Sung Kwak KR; Sang Hyun Ryu KR, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  173. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  174. Yee, Jae Hak; Chung, Young Suk; Lee, Jae Jin; Davis, Terry; Han, Chung Suk; Ku, Jae Hun; Kwak, Jae Sung; Ryu, Sang Hyun, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
  175. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  176. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  177. Lee, Sun Goo; Jang, Sang Jae; Lee, Choon Heung; Yoshida, Akito, Semiconductor package capable of die stacking.
  178. Lee, Sun Goo; Lee, Choon Heung; Lee, Sang Ho, Semiconductor package exhibiting efficient lead placement.
  179. Tao Su,TWX ; Lo Kuang-Lin,TWX ; Wei Hsin-Hsing,TWX, Semiconductor package having a heat spreader capable of preventing being soldered and enhancing adhesion and electrical performance.
  180. Lin, Pang-Chun; Li, Chun-Yuan; Tang, Fu-Di; Huang, Chien-Ping; Ke, Chun-Chi, Semiconductor package having electrical connecting structures and fabrication method thereof.
  181. Lin, Pang-Chun; Li, Chun-Yuan; Tang, Fu-Di; Huang, Chien-Ping; Ke, Chun-Chi, Semiconductor package having electrical connecting structures and fabrication method thereof.
  182. Jang, Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  183. Jang,Sung Sik, Semiconductor package having improved adhesiveness and ground bonding.
  184. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  185. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  186. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  187. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
  188. Paek, Jong Sik, Semiconductor package including flip chip.
  189. Paek,Jong Sik, Semiconductor package including flip chip.
  190. Shin Won Sun,KRX ; Lee Won Kyun,KRX, Semiconductor package including heat sink with layered conductive plate and non-conductive tape bonding to leads.
  191. Foster, Donald Craig, Semiconductor package including isolated ring structure.
  192. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
  193. Yang, Jun Young; Lee, Sun Goo; Lee, Choon Heung, Semiconductor package including low temperature co-fired ceramic substrate.
  194. Miks, Jeffrey Alan, Semiconductor package including ring structure connected to leads with vertically downset inner ends.
  195. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package including stacked chips with aligned input/output pads.
  196. Yu, Cheng-Hsien; Hsu, Wen Tsung; Tsai, Chun Yuan, Semiconductor package including substrates spaced by at least one electrical connecting element.
  197. Yang,Sung Jin; Ha,Sun Ho; Kim,Ki Ho; Son,Sun Jin, Semiconductor package with chamfered corners and method of manufacturing the same.
  198. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  199. Perez, Erasmo; Roman, David T., Semiconductor package with exposed die pad and body-locking leadframe.
  200. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
  201. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
  202. Yin, Cha-Yun; Laio, Ming-Chun; Tang, Fu-Di; Huang, Chien-Ping, Semiconductor package with heat dissipating structure.
  203. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
  204. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
  205. Lee, Choon Heung; Foster, Donald C.; Choi, Jeoung Kyu; Kim, Wan Jong; Youn, Kyong Hoon; Lee, Sang Ho; Lee, Sun Goo, Semiconductor package with increased number of input and output pins.
  206. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
  207. Jeong, Jung Ho; Hong, Jong Chul; Kim, Eun Deok, Semiconductor package with optimized leadframe bonding strength.
  208. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
  209. Hu, Tom; Davis, Terry W.; Bancod, Ludovico, Semiconductor package with singulation crease.
  210. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  211. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  212. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
  213. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
  214. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
  215. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
  216. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
  217. Lau,Daniel K.; Law,Edward L. T., Thermal enhanced package for block mold assembly.
  218. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  219. McCann,David R.; Groover,Richard L.; Hoffman,Paul R., Thermally enhanced chip scale lead on chip semiconductor package and method of making same.
  220. Railkar, Tarak A.; Cate, Steven D., Thermally enhanced semiconductor package.
  221. Viswanath Ram S. ; Maxwell Martin M. ; Shahriari Navid, Thermally enhanced test contactor.
  222. Viswanath Ram S. ; Maxwell Martin M., Thermally enhanced test socket.
  223. McLellan,Neil; Pedron,Serafin; Higgins, III,Leo M.; Tsang,Kwok Cheung; Kwan,Kin Pui, Thin array plastic package without die attach pad and process for fabricating the same.
  224. Dunlap, Brett Arnold; Copia, Alexander William, Thin stackable package and method.
  225. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  226. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  227. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  228. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  229. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  230. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
  231. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  232. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  233. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  234. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  235. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  236. Zimmerman, Michael, Ultra high-temperature plastic package and method of manufacture.
  237. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  238. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  239. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  240. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  241. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  242. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  243. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  244. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  245. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
  246. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로