[특허]Scalable architecture for asynchronous transfer mode segmentation and reassembly

[미국특허] Scalable architecture for asynchronous transfer mode segmentation and reassembly 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H04L-012/28 H04L-012/56
출원번호	US-0522432 (1995-08-31)
발명자 / 주소	Christensen Soeren S. (Santa Clara CA)
출원인 / 주소	Sun Microsystems, Inc. (Mountain View CA 02)
인용정보	피인용 횟수 : 54 인용 특허 : 6

초록 ▼

A scalable, asynchronous transfer mode (“ATM”) interface for generating an ATM cell comprising an addressing element, a memory element and a cell generating element. The addressing element is used to initiate generation of the ATM cell by transmitting one or more memory addresses to the memory element. The memory element, accessible to the addressing element, is used to store at least one datagram corresponding to the memory address(es) and to subsequently output the at least one datagram to the cell generating element. The cell generating element is coupled to the memory element in order to receive at least one datagram and produce the ATM cell. Finally, a controlling element is coupled to the addressing element and the cell generating element in order to control their operations.

대표청구항 ▼

A scalable, asynchronous transfer mode (“ATM”) interface, comprising: an addressing element including a scheduler configured to initiate generation of an ATM cell, and an address generator coupled to said scheduler, said address generator is configured to receive at least one channel number from said scheduler, and to translate said at least one channel number into at least one memory address; a memory element accessible by said addressing element, said memory element is configured to contain at least one datagram corresponding to said at least one memory address; a cell generating element coupled to said memory element, said cell generating element is configured to receive said at least one datagram and to produce said ATM cell including a header and a payload including said at least one datagram; and a controlling element coupled to said scheduler and address generator of said addressing element and said cell generating element, said controlling element is configured to control the operations of said addressing element and said cell generating element.

이 특허에 인용된 특허 (6) 인용/피인용 타임라인 분석

Nishino Tetsuo (Kawasaki JPX) Eda Susumu (Kawasaki JPX) Hyodo Ryuji (Kawasaki JPX) Oomuro Katsumi (Kawasaki JPX) Sekihata Osamu (Kawasaki JPX) Tanaka Kenji (Kawasaki JPX) Hatta Hiroyuki (Kawasaki JPX, ATM cell assembling and disassembling system and method.
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Yamashita Hiroshi (Tokyo JPX), ATM cell format conversion system.
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Ohno Koichi (Yokohama JPX) Tachibana Tetsuo (Kawasaki JPX), Apparatus for controlling ATM cell generation rate.
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Punj Vikram (Naperville IL), Channel adapter for broadband communications at channel speeds.
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Hedlund Kurt A. (Chicago IL), Hardware interface to a high-speed multiplexed link.
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Traw Brendan S. (Bridgewater MA) Smith Jonathan M. (Metuchen NJ), High-performance host interface for ATM networks.
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이 특허를 인용한 특허 (54) 인용/피인용 타임라인 분석

Daniel Thomas ; Nattkemper Dieter ; Varma Subir, ATM communication system interconnect/termination unit.
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Daniel Thomas ; Nattkemper Dieter ; Varma Subir, ATM communication system interconnect/termination unit.
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Daniel, Thomas; Nattkemper, Dieter; Varma, Subir, ATM communication system interconnect/termination unit.
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Norton Kenneth ; Rumer Mark, ATM switch with integrated system bus.
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Song Doug-Young,KRX, ATM switching system supporting N-ISDN traffic and method for controlling the same.
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Cao, Carl F.; Liu, Yajun; Wijayanathan, Maiyuran, Apparatus and method for channel assignment of packet flows.
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Thomas Robert E. ; Roman Peter J. ; Cheung Wing, Apparatus and method for performing look-ahead scheduling of DMA transfers of data from a host memory to a transmit bu.
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Jeffrey R. Gemar, Apparatus and method for proving multiple and simultaneous quality of service connects in a tunnel mode.
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Jeffrey R. Gemar ; Warner B. Andrews, Jr., Apparatus and method for scheduling multiple and simultaneous traffic in guaranteed frame rate in ATM communication system.
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Thomas Robert E. ; Simcoe Robert J. ; Roman Peter J. ; Charny Anna ; Cheung Wing, Apparatus and method for scheduling virtual circuit data for DMA from a host memory to a transmit buffer memory.
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Tanaka Koichi,JPX ; Roman Peter J. ; Abe Kohei,JPX ; Mizuguchi Shinichi,JPX, Apparatus and method for setting a congestion indicate bit in an backwards RM cell on an ATM network.
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Thomas Robert E. ; Roman Peter J. ; Cheung Wing, Apparatus and method for transferring data from a transmit buffer memory at a particular rate.
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Jong Arm Jun KR; Chan Kim KR; Yeong Ho Park KR; Ik Kyun Kim KR; Young Wook Cha KR; Kyou Ho Lee KR; Hyup Jong Kim KR; Jae Geun Kim KR, Asynchronous transfer mode host adapter apparatus with ability of shared media access.
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Branstad, Mark William; Byrn, Jonathan William; Delp, Gary Scott; Leichty, Philip Lynn; Leonard, Todd Edwin; McClannahan, Gary Paul; Nordman, John Emery; Plotz, Kevin Gerard; Shaffer, John Handley; S, Communications adapter for implementing communications in a network and providing multiple modes of communications.
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Leichty Philip Lynn ; Slane Albert Alfonse, Communications cell scheduler and scheduling method for providing periodic activities.
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Fraser Alexander Gibson, Customer telecommunication interface device with built-in network features.
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Kawakami, Daisuke, Data transfer and alignment device and method for transferring data acquired from memory.
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Barash, Dror, Determining data transmission error and/or checking or confirming such error determinations.
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Chow Kit Man ; Nguyen Chinh Kim, Enhanced interface for an asynchronous transfer mode segmentation controller.
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Rostoker Michael D. ; Stelliga D. Tony, Error detection and correction apparatus for an asynchronous transfer mode (ATM) network device.
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Li Kwok-Leung ; Ho Yung-Lung, Error tolerant addressing system and method for noisy ATM links.
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Oskouy, Rasoul Mirzazadeh; Ferguson, Dennis C.; Ju, Hann-Hwan; Lim, Raymond Marcelino Manese; Sindhu, Pradeep S.; Veeragandham, Sreeram; Zimmer, Jeff; Hui, Michael M. Y., In-line packet processing.
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Oskouy, Rasoul Mirzazadeh; Ferguson, Dennis C.; Ju, Hann-Hwan; Lim, Raymond Marcelino Manese; Sindhu, Pradeep S.; Veeragandham, Sreeram; Zimmer, Jeff; Hui, Michael M. Y., In-line packet processing.
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Oskouy, Rasoul Mirzazadeh; Ferguson, Dennis C.; Ju, Hann-Hwan; Lim, Raymond Marcelino Manese; Sindhu, Pradeep S.; Veeragandham, Sreeram; Zimmer, Jeff; Hui, Michael M. Y., In-line packet processing.
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Oskouy, Rasoul Mirzazadeh; Ferguson, Dennis C.; Ju, Hann-Hwan; Lim, Raymond Marcelino Manese; Sindhu, Pradeep S.; Veeragandham, Sreeram; Zimmer, Jeff; Hui, Michael M. Y., In-line packet processing.
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Oskouy, Rasoul Mirzazadeh; Ferguson, Dennis C; Ju, Hann-Hwan; Lim, Raymond Marcelino Manese; Sindhu, Pradeep S; Veeragandham, Sreeram; Zimmer, Jeff; Hui, Michael M. Y., In-line packet processing.
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B. Scott Darnell ; William T. Jennings ; Bradley D. Lengel ; Praveen S. Reddy, METHOD FOR MANAGING STORAGE OF DATA BY STORING BUFFER POINTERS OF DATA COMPRISING A SEQUENCE OF FRAMES IN A MEMORY LOCATION DIFFERENT FROM A MEMORY LOCATION FOR POINTERS OF DATA NOT COMPRISING A SEQU.
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Thomas Robert E. ; Washabaugh Douglas M. ; Roman Peter J. ; Cheung Wing, Method and apparatus for avoiding control reads in a network node.
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Thomas Robert E. ; Washabaugh Douglas M. ; Roman Peter J. ; Cheung Wing, Method and apparatus for avoiding control reads in a network node.
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Timbs Jeffrey L., Method and apparatus for converting data streams in a cell based communications system.
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Delp Gary Scott ; Slane Albert Alfonse, Method and apparatus for enhanced scatter mode allowing user data to be page aligned.
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Thomas Robert E. ; Ross Theodore L. ; Washabaugh Douglas M. ; Roman Peter J. ; Cheung Wing ; Tanaka Koichi,JPX ; Mizuguchi Shinichi,JPX, Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network.
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Theodore L. Ross ; Douglas M. Washabaugh ; Peter J. Roman ; Wing Cheung ; Koichi Tanaka JP; Shinichi Mizuguchi JP; Robert E. Thomas, Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node.
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Craig S. Rich, Method and apparatus for providing a serial interface between an asynchronous transfer mode (ATM) layer and a physical (PHY) layer.
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Rich Craig S., Method and apparatus for regenerating a control signal at an asynchronous transfer mode (ATM) layer or a physical (PHY).
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Darnell B. Scott ; Jennings William T. ; Lengel Bradley D. ; Reddy Praveen S., Method and apparatus to insert and extract data from a plurality of slots of data frames by using access table to identify network nodes and their slots for insertion and extraction data.
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Darnell B. Scott ; Jennings William T. ; Lengel Bradley D. ; Reddy Praveen S., Method and system for communicating information in a network.
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B. Scott Darnell ; William T. Jennings ; Bradley D. Lengel ; Praveen S. Reddy, Method and system for scheduling network communication.
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Darnell,B. Scott; Jennings,William T.; Lengel,Bradley D.; Reddy,Praveen S., Method and system for scheduling network communication.
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Barash,Dror, Methods, architectures, circuits, software and systems for CRC determination.
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Barash,Dror, Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations.
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Gotesman Joel ; Gritton Gregory Vance, Programmable reassembly of data received in an ATM network.
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Lincoln Bradford C., Scheduler utilizing dynamic schedule table.
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Lincoln Bradford C., Scheduler utilizing dynamic schedule table.
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Thomas Daniel ; Dieter Nattkemper ; Subir Varma, Single chip networking device with enhanced memory access co-processor.
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Wright, Ian M., Stage specific dilation in multi-stage interconnection networks.
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Harish N. Mathur, Store-and-forward network switch using an embedded DRAM.
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Andersson,Leif Arne Jorgen; Fullemann,John, Synchronous data transfer system for time-sensitive data in packet-switched networks.
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Gutierrez,Maria C.; Clayton,Shawn Adam; Follett,David R.; Roman,Harold E.; Godiwala,Nitin D.; Prohaska,Richard F.; Williams,James B., System and method for regulating message flow in a digital data network.
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Clayton, Shawn A.; Follett, David R.; Godiwala, Nitin D.; Gutierrez, Maria C.; Wells, David S.; Williams, James B., System and method for scheduling message transmission and processing in a digital data network.
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Clayton,Shawn A.; Follett,David R.; Godiwala,Nitin D.; Gutierrez,Maria C.; Wells,David S.; Williams,James B., System and method for scheduling message transmission and processing in a digital data network.
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Rosenberg Jonathan David, System for emulating a virtual path in an ATM network.
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Lincoln, Bradford C.; Meyer, David R., System for, and method of, ATM segmentation and re-assembly of cells providing streaming data.
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Martinsson Lars Olle,SEX, Timing and synchronization technique for ATM system.
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[미국특허] Scalable architecture for asynchronous transfer mode segmentation and reassembly 원문보기